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2013 IEEE 43rd International Symposium on Multiple-Valued Logic最新文献

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Secure Key Storage Using State Machines 使用状态机的安全密钥存储
2013 IEEE 43rd International Symposium on Multiple-Valued Logic Pub Date : 2013-05-22 DOI: 10.1109/ISMVL.2013.50
Nan Li, S. Mansouri, E. Dubrova
{"title":"Secure Key Storage Using State Machines","authors":"Nan Li, S. Mansouri, E. Dubrova","doi":"10.1109/ISMVL.2013.50","DOIUrl":"https://doi.org/10.1109/ISMVL.2013.50","url":null,"abstract":"In hardware implementations of cryptographic systems, secret keys are commonly stored in an on-chip memory. This makes them prone to physical attacks, since the location of a memory on a chip in usually easy to spot. We propose to encode secret keys using a state machine which can be concealed in the rest of the logic on a chip. We present an heuristic algorithm which constructs a minimal state machine for a given set of secret keys. We show that, by using m-ary encoding, we are able to construct state machines which are smaller than the ones constructed using binary encoding. The presented algorithm is feasible for storing up to 1 Mbits of random data.","PeriodicalId":124947,"journal":{"name":"2013 IEEE 43rd International Symposium on Multiple-Valued Logic","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133304268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Gaze Estimation Using Electrooculogram Signals and Its Mathematical Modeling 基于眼电信号的注视估计及其数学建模
2013 IEEE 43rd International Symposium on Multiple-Valued Logic Pub Date : 2013-05-22 DOI: 10.1109/ISMVL.2013.31
Mingmin Yan, H. Tamura, K. Tanno
{"title":"Gaze Estimation Using Electrooculogram Signals and Its Mathematical Modeling","authors":"Mingmin Yan, H. Tamura, K. Tanno","doi":"10.1109/ISMVL.2013.31","DOIUrl":"https://doi.org/10.1109/ISMVL.2013.31","url":null,"abstract":"The aim of this study is to present electrooculogram signals that can be used for human computer interface efficiently. Establishing an efficient alternative channel for communication without overt speech and hand movements is important to increase the quality of life for patients suffering from Amyotrophic Lateral Sclerosis or other illnesses that prevent correct limb and facial muscular responses. In this paper, we introduce the gaze estimation system of electrooculogram signals. Using this system, the electrooculogram signals can be recorded when the patients focused on each direct. All these recorded signals could be analyzed using math-method and the mathematical model will be set up. Gaze estimation can be recognized using electrooculogram signals follow these models.","PeriodicalId":124947,"journal":{"name":"2013 IEEE 43rd International Symposium on Multiple-Valued Logic","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134079560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A Successive Approximation A/D Converter Using Generalized Non-Binary Algorithm 基于广义非二进制算法的逐次逼近A/D转换器
2013 IEEE 43rd International Symposium on Multiple-Valued Logic Pub Date : 2013-05-22 DOI: 10.1109/ISMVL.2013.9
Yu Kurisu, T. Sasaki, T. Waho
{"title":"A Successive Approximation A/D Converter Using Generalized Non-Binary Algorithm","authors":"Yu Kurisu, T. Sasaki, T. Waho","doi":"10.1109/ISMVL.2013.9","DOIUrl":"https://doi.org/10.1109/ISMVL.2013.9","url":null,"abstract":"An 8-bit successive approximation analog-to-digital converter (SA ADC) has been designed and fabricated by using a 0.18-μm technology. A generalized non-binary algorithm has been used to enhance operation speed by relaxing the settling constraint of the DAC output. A split-capacitor array with a monotonic switching scheme has also been incorporated to reduce the power consumption. Transistor-level simulation shows an effective number of bits (ENOB) of 7.91 bits under a Nyquist condition with a sampling frequency of 2 MHz. Fabricated chip operates successfully, proving the design principle.","PeriodicalId":124947,"journal":{"name":"2013 IEEE 43rd International Symposium on Multiple-Valued Logic","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132024717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Fuzzy Damage Extraction Method for Ultrasonic Nondestructive Testing Images 超声无损检测图像的模糊损伤提取方法
2013 IEEE 43rd International Symposium on Multiple-Valued Logic Pub Date : 2013-05-22 DOI: 10.1109/ISMVL.2013.30
Koki Tsukuda, Tadahito Egawa, K. Taniguchi, Kei Kuramoto, Syoji Kobashi, Y. Hata
{"title":"Fuzzy Damage Extraction Method for Ultrasonic Nondestructive Testing Images","authors":"Koki Tsukuda, Tadahito Egawa, K. Taniguchi, Kei Kuramoto, Syoji Kobashi, Y. Hata","doi":"10.1109/ISMVL.2013.30","DOIUrl":"https://doi.org/10.1109/ISMVL.2013.30","url":null,"abstract":"This paper describes fuzzy damage extraction method for ultrasonic nondestructive testing images. In our experiment, we employ a piece of wind turbine blade as a specimen has artificial damages. We acquire ultrasonic waveforms from scanning lines on surface of the pecimen using an ultrasonic single probe. To extract the damages, we calculate fuzzy degrees of average difference data of all scanning lines, and make fuzzy images whose ntensities calculated by the fuzzy degrees. As the results, we found the line image with all damage portions, and we estimated depth of damage surface with high accuracy.","PeriodicalId":124947,"journal":{"name":"2013 IEEE 43rd International Symposium on Multiple-Valued Logic","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123189836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
On the Clones Containing a Near-Unanimity Function 关于包含近一致函数的克隆
2013 IEEE 43rd International Symposium on Multiple-Valued Logic Pub Date : 2013-05-22 DOI: 10.1109/ISMVL.2013.46
Dmitriy Zhuk, S. Moiseev
{"title":"On the Clones Containing a Near-Unanimity Function","authors":"Dmitriy Zhuk, S. Moiseev","doi":"10.1109/ISMVL.2013.46","DOIUrl":"https://doi.org/10.1109/ISMVL.2013.46","url":null,"abstract":"In previous papers we introduced the notion of an essential predicate, that is a predicate that cannot be presented as a conjunction of predicates with smaller arities. We showed that all clones of functions can be defined by a set of essential predicates. We introduced several operations on the set of essential predicates and defined a closure operator under these operations. There exists a one-to-one correspondence (a Galois connection) between clones and closed sets of essential predicates. Thus, these closed sets provide a valuable tool to studying clones. If the closure of a set of essential predicates is finite then it can be calculated using a computer. As it follows from Baker-Pixley theorem, a closed set corresponding to a clone is finite if and only if the clone contains a near-unanimity function. In the paper we present an approach to constructing a lattice of clones containing a given near-unanimity function. Particularly, all clones on three elements containing a majority function were calculated by a computer program. There turned out to be 1 918 040 clones. To analyze the possibility of constructing the lattices of clones in other cases, we give estimates on the number of clones containing a near-unanimity function of arity n. Also we prove estimates on the maximal size of a chain of clones containing a near-unanimity function. We conclude that it is impossible in practice to obtain the description for clones on four elements, as well as for a near-unanimity function of arity four.","PeriodicalId":124947,"journal":{"name":"2013 IEEE 43rd International Symposium on Multiple-Valued Logic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127795875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Ternary Logic Network Justification Using Transfer Matrices 使用传递矩阵的三元逻辑网络论证
2013 IEEE 43rd International Symposium on Multiple-Valued Logic Pub Date : 2013-05-22 DOI: 10.1109/ISMVL.2013.57
M. Thornton, Jennifer Dworak
{"title":"Ternary Logic Network Justification Using Transfer Matrices","authors":"M. Thornton, Jennifer Dworak","doi":"10.1109/ISMVL.2013.57","DOIUrl":"https://doi.org/10.1109/ISMVL.2013.57","url":null,"abstract":"A linear algebraic method is developed that allows for logic network justification problems to be solved. The method differs from previous techniques that require learning or solution space search techniques in that all possible justification solutions are determined through a single vector-matrix product calculation. The logic network is represented by a matrix that is defined as the \"justification\" matrix. It is shown that the justification matrix is simply the transpose of the network transfer matrix and is thus easily obtained through a traversal of the network netlist. Example justification calculations are provided.","PeriodicalId":124947,"journal":{"name":"2013 IEEE 43rd International Symposium on Multiple-Valued Logic","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116189485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Tense Operators and Dynamic De Morgan Algebras 紧算子与动态De Morgan代数
2013 IEEE 43rd International Symposium on Multiple-Valued Logic Pub Date : 2013-05-22 DOI: 10.1109/ISMVL.2013.56
I. Chajda, Jan Paseka
{"title":"Tense Operators and Dynamic De Morgan Algebras","authors":"I. Chajda, Jan Paseka","doi":"10.1109/ISMVL.2013.56","DOIUrl":"https://doi.org/10.1109/ISMVL.2013.56","url":null,"abstract":"To every propositional logic satisfying double negation law is assigned a De Morgan poset ε. Using of axioms for an universal quantifier, we set up axioms for the so-called tense operators G and H on ε. The triple D = (ε; G, H) is called a (partial) dynamic De Morgan algebra. We solve the following questions: first, if a time frame is given, how to construct tense operators G and H; second, if a dynamic De Morgan algebra is given, how to find a time frame such that its tense operators G and H can be reached by this construction.","PeriodicalId":124947,"journal":{"name":"2013 IEEE 43rd International Symposium on Multiple-Valued Logic","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131633918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
On Synthesis and Verification from Event Diagrams in a Robot Theatre Application 事件图在机器人剧场应用中的综合与验证
2013 IEEE 43rd International Symposium on Multiple-Valued Logic Pub Date : 2013-05-22 DOI: 10.1109/ISMVL.2013.45
M. Perkowski, Aditya Bhutada, M. Lukac, Mathias Sunardi
{"title":"On Synthesis and Verification from Event Diagrams in a Robot Theatre Application","authors":"M. Perkowski, Aditya Bhutada, M. Lukac, Mathias Sunardi","doi":"10.1109/ISMVL.2013.45","DOIUrl":"https://doi.org/10.1109/ISMVL.2013.45","url":null,"abstract":"We present a new type of expressions called Event Expressions (EE), and diagrams called Event Diagrams (ED), that are used to describe robot behaviors (motions). These diagrams are very general and include operators from many known representations, such as Regular Expressions, Boolean and Fuzzy Logic plus many new operators. Most importantly, EDs create probability operator counterparts for all these deterministic operators. They can be used for event acceptance or event generation. The diagrams are intended to simulate robot controllers and verify their correctness and properties.","PeriodicalId":124947,"journal":{"name":"2013 IEEE 43rd International Symposium on Multiple-Valued Logic","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126305401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Dramatically Low-Transistor-Count High-Speed Ternary Adders 显著低晶体管计数高速三元加法器
2013 IEEE 43rd International Symposium on Multiple-Valued Logic Pub Date : 2013-05-22 DOI: 10.1109/ISMVL.2013.24
R. F. Mirzaee, M. H. Moaiyeri, Mojtaba Maleknejad, K. Navi, O. Hashemipour
{"title":"Dramatically Low-Transistor-Count High-Speed Ternary Adders","authors":"R. F. Mirzaee, M. H. Moaiyeri, Mojtaba Maleknejad, K. Navi, O. Hashemipour","doi":"10.1109/ISMVL.2013.24","DOIUrl":"https://doi.org/10.1109/ISMVL.2013.24","url":null,"abstract":"Ternary logic has inherently the potential of high computational speed in comparison with conventional binary logic. A new low-transistor-count, high-speed ternary half adder is presented in this paper. Carbon nanotube field effect transistors are utilized to realize the new design methodology. Unique characteristics of this technology provide multi-Vt circuitry with the flexibility which is highly essential for MVL designs. The given structure also benefits from high driving power and capability of operating in low voltages. It has only 26 transistors. A new high-performance ternary full adder is also presented. Finally, the proposed adder cells are put together in order to construct a 4-bit ternary ripple adder.","PeriodicalId":124947,"journal":{"name":"2013 IEEE 43rd International Symposium on Multiple-Valued Logic","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129639173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
Accurate and High-Speed Asynchronous Network-on-Chip Simulation Using Physical Wire-Delay Information 基于物理线延迟信息的精确高速异步片上网络仿真
2013 IEEE 43rd International Symposium on Multiple-Valued Logic Pub Date : 2013-05-22 DOI: 10.1109/ISMVL.2013.11
T. Hanyu, Y. Watanabe, Atsushi Matsumoto
{"title":"Accurate and High-Speed Asynchronous Network-on-Chip Simulation Using Physical Wire-Delay Information","authors":"T. Hanyu, Y. Watanabe, Atsushi Matsumoto","doi":"10.1109/ISMVL.2013.11","DOIUrl":"https://doi.org/10.1109/ISMVL.2013.11","url":null,"abstract":"A performance-evaluation simulator is a key tool for exploring appropriate asynchronous Network-on-Chip (NoC) architecture in early stage of LSI design. This paper presents a highly accurate performance-evaluation simulator with maintaining a short evaluation time for designing a high-performance asynchronous NoC. The use of a precise asynchronous-router circuit model, whose physical parameters such as wire delays as well as unit gate delays are preliminarily obtained using LSI CAD tool, makes it accurate to simulate asynchronous NoC systems. As a design example, multi-core asynchronous mesh-structured NoC systems are simulated by both the previous method and the proposed one whose results, such as latency and throughput, are validated with a highly precise transistor-level simulation result. As a result, the proposed simulator achieves almost the same accuracy as the corresponding gate-level simulators, while its simulation speed is one-thousand-times faster than that of the gate-level one at the packet injection rate of 30 (packets/μsec).","PeriodicalId":124947,"journal":{"name":"2013 IEEE 43rd International Symposium on Multiple-Valued Logic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129654812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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