发布求助
文献互助 智能选刊 最新文献

Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair最新文献

筛选
英文 中文
Silicon single-electron transistors on a SIMOX substrate SIMOX衬底上的硅单电子晶体管
Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair Pub Date : 1995-08-29 DOI: 10.1109/ASPDAC.1995.486389
K. Murase, Y. Talahashi, A. Fujiwara, M. Nagase, M. Tabe
{"title":"Silicon single-electron transistors on a SIMOX substrate","authors":"K. Murase, Y. Talahashi, A. Fujiwara, M. Nagase, M. Tabe","doi":"10.1109/ASPDAC.1995.486389","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486389","url":null,"abstract":"Until recently, single-electron transistors have only been operable at very low temperatures, mostly below 1 K. By contrast, Si single-electron transistors fabricated on a SIMOX substrate by using a pattern-dependent oxidation technique show conductance oscillations even at room temperature. In addition, a single-electron memory effect is observed in specially designed Si single-electron transistors.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133582513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Multi-level equivalence in design transformation 设计转换中的多层次等价
Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair Pub Date : 1995-08-29 DOI: 10.1109/ASPDAC.1995.486370
T.K.-Y. Cheung, G. Hellestrand
{"title":"Multi-level equivalence in design transformation","authors":"T.K.-Y. Cheung, G. Hellestrand","doi":"10.1109/ASPDAC.1995.486370","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486370","url":null,"abstract":"This paper introduces the notion of multi-level equivalence in transformational synthesis of hardware or software. Two distinct, but interrelated levels of equivalence (behaviour and function-equivalence) are supported in this formalism. This would allow either or both the behaviour and functionality of the original function specification to be preserved during automatic synthesis which is typically based on a series of applications of equivalent transformation mechanisms. In essence, this formalism makes possible the evolution of behaviours while maintaining the functionality. This has extended the traditional view of synthesis through refinement to synthesis through exploration and evolution.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"243 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134056993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
An intelligent, self-deducing graphical register transfer interface based on a distributed constraint logic computation 一个基于分布式约束逻辑计算的智能、自演绎的图形寄存器传输接口
Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair Pub Date : 1995-08-29 DOI: 10.1109/ASPDAC.1995.486373
G. Jennings
{"title":"An intelligent, self-deducing graphical register transfer interface based on a distributed constraint logic computation","authors":"G. Jennings","doi":"10.1109/ASPDAC.1995.486373","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486373","url":null,"abstract":"We present a graphical capture tool for register transfer level modeling which is capable of deducing bus widths and other such undeclared circuit parameters with minimal user intervention. Known design parameters are self-propagated over the entire circuit, and can lead for example to all undeclared bus widths becoming automatically defined. This frees the designer from explicitly declaring those circuit features which the tool can deduce. Furthermore this provides fully generic n-bit m-input components, such as \"wide flip-flops\" having uncommitted width, at that point in the design cycle when such constructs are most needed. The novel use of constraints within individual model elements, together with a distributed constraint logic computation, provides the deductive mechanism. We describe the facility and examine its performance on a number of test cases.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132055579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Generic fuzzy logic CAD development tool 通用模糊逻辑CAD开发工具
Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair Pub Date : 1995-08-01 DOI: 10.1109/ASPDAC.1995.486205
E. Q. Kang, E. Shragowitz
{"title":"Generic fuzzy logic CAD development tool","authors":"E. Q. Kang, E. Shragowitz","doi":"10.1109/ASPDAC.1995.486205","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486205","url":null,"abstract":"This paper describes a generic fuzzy logic CAD development tool and reports on application of it to some important CAD problems. This menu-based tool allows to introduce linguistic variables in a textual and graphic form by clicking a menu. It permits users to define membership functions in an analytical, table or graphical forms. It connects linguistic variables by fuzzy logic operators to create fuzzy logic and generates their graphical representations.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117157529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Communication based FPGA synthesis for multi-output Boolean functions 基于通信的多输出布尔函数的FPGA合成
Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair Pub Date : 1995-08-01 DOI: 10.1109/ASPDAC.1995.486235
Christoph Scholl, P. Molitor
{"title":"Communication based FPGA synthesis for multi-output Boolean functions","authors":"Christoph Scholl, P. Molitor","doi":"10.1109/ASPDAC.1995.486235","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486235","url":null,"abstract":"One of the crucial problems multi level logic synthesis techniques for multi output Boolean functions f=(f/sub 1/,...,f/sub m/):{0,1}/sup n//spl rarr/{0,1}/sup m/ have to deal with is finding sublogic which can be shared by different outputs, i.e., finding Boolean functions /spl alpha/=(/spl alpha//sub 1/,...,/spl alpha//sub h/):{0,1}/sup p//spl rarr/{0,1}/sup h/ which can be used as common sublogic of good realizations of f/sub 1/,...,f/sub m/. We present an efficient ROBDD based implementation of this common decomposition functions problem (CDF). Formally, CDF is defined as follows: given m Boolean functions f/sub 1/,...,f/sub m/:{0,1}/sup n//spl rarr/{0,1}, and two natural numbers p and h, find h Boolean functions /spl alpha//sub 1/,..., /spl alpha//sub h/:{0, 1}/sup p//spl rarr/{0,1} such that /spl forall/1/spl les/k/spl les/m there is a decomposition of f/sub k/ of the form: f/sub k/(x/sub 1/,...x/sub n/)=g/sup (k)/(/spl alpha//sub 1/(x/sub 1/,...x/sub p/),...,/spl alpha//sub h/(x/sub 1/,...,x/sub p/),/spl alpha//sub h+1//sup (k)/(x/sub 1/,...,x/sub p/),...,/spl alpha/(r/sub k/)/sup (k)/(x/sub 1/,...x/sub p/),x/sub p+1/,...,x/sub n/) using a minimal number r/sub k/ of single output Boolean decomposition functions. Experimental results applying the method to FPGA synthesis are promising.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"639 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114049386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A new and accurate interconnection delay time evaluation in a general tree-type network 一种新的、准确的树型网络互连时延评估方法
Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair Pub Date : 1995-08-01 DOI: 10.1109/ASPDAC.1995.486246
D. Deschacht, C. Dabrin
{"title":"A new and accurate interconnection delay time evaluation in a general tree-type network","authors":"D. Deschacht, C. Dabrin","doi":"10.1109/ASPDAC.1995.486246","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486246","url":null,"abstract":"In all recent technologies the delay caused by interconnection wires is essential in the evaluation of the switching speed of integrated structures. Completely wrong results would result if this were neglected. By considering a distributed RC network to model the interconnection lines, we proposed a new analytical delay time expression for a general tree type network, with full incorporation of technology design parameters. A computationally simple technique is presented and comparisons with HSPICE simulation results show the accuracy of the developed model in timing verification.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126979253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High-level synthesis scheduling and allocation using genetic algorithms 基于遗传算法的高级综合调度与分配
Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair Pub Date : 1995-08-01 DOI: 10.1109/ASPDAC.1995.486203
M. Heijligers, L.J.M. Cluitmans, J.A.G. Jess
{"title":"High-level synthesis scheduling and allocation using genetic algorithms","authors":"M. Heijligers, L.J.M. Cluitmans, J.A.G. Jess","doi":"10.1109/ASPDAC.1995.486203","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486203","url":null,"abstract":"In this article a scheduling method is presented which is capable of allocating supplementary resources during scheduling. This makes it very suitable in synthesis strategies based on lower bound estimations techniques. The method is based on genetic algorithms. Special coding techniques and analysis methods are used to improve the runtime and quality of the results. The scheduler can easily be extended to cover other architectural issues and (for example) provides ways to make trade-offs between functional unit allocation and register allocation. Experiments and comparisons show high quality results and fast run times that outperform results produced by other heuristic scheduling methods.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124499730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 57
Delay abstraction in combinational logic circuits 组合逻辑电路中的延迟抽象
Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair Pub Date : 1995-08-01 DOI: 10.1109/ASPDAC.1995.486355
Noriya Kobayashi, S. Malik
{"title":"Delay abstraction in combinational logic circuits","authors":"Noriya Kobayashi, S. Malik","doi":"10.1109/ASPDAC.1995.486355","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486355","url":null,"abstract":"In this paper we propose a data structure for abstracting the delay information of a combinatorial circuit. The particular abstraction that we are interested in is one that preserves the delays between all pairs of inputs and outputs in the circuit. The proposed graphical data structure is of size proportional to (m+n) in best case, where m and n refer to the number of inputs and outputs of the circuit. In comparison, a delay matrix that stores the maximum delay between each input/output pair has size proportional to m/spl times/n. We present heuristic algorithms for deriving these concise delay networks. Experimental results shows that, in practice, we can obtain concise delay network with the number of edges being a small multiple of (m+n).","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134313558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A hardware-oriented design for weighted median filters 一种面向硬件的加权中值滤波器设计
Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair Pub Date : 1995-08-01 DOI: 10.1109/ASPDAC.1995.486352
Chun-Te Chen, Liang-Gee Chen, Jue-Hsuan Hsiao
{"title":"A hardware-oriented design for weighted median filters","authors":"Chun-Te Chen, Liang-Gee Chen, Jue-Hsuan Hsiao","doi":"10.1109/ASPDAC.1995.486352","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486352","url":null,"abstract":"In this paper, the design consideration and algorithm mapping for weighted median filters are presented. To achieve high throughput rate, a special coding technique and its dedicated architecture with block processing are constructed to handle multiple filtering inputs and outputs concurrently. The pipelined cycle in our design has the delay time of 1-bit carry-save-adder (CSA). Due to this design strategy, the proposed architecture can support not only weighted median filters but also rank order-based filters in high-speed applications.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131487594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Optimization methods for lookup-table-based FPGAs using Transduction Method 基于转导法的查找表fpga优化方法
Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair Pub Date : 1995-08-01 DOI: 10.1109/ASPDAC.1995.486245
S. Yamashita, Y. Kambayashi, S. Muroga
{"title":"Optimization methods for lookup-table-based FPGAs using Transduction Method","authors":"S. Yamashita, Y. Kambayashi, S. Muroga","doi":"10.1109/ASPDAC.1995.486245","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486245","url":null,"abstract":"In recent years Field Programmable Gate Arrays (FPGAs) have emerged as an attractive means to implement low volume applications and prototypes due to their low cost, reprogrammability and rapid turnaround times. Therefore, the need for design methods of FPGAs are getting larger and larger. In this paper, two methods to optimize networks which have been mapped for lookup-table-based FPGAs are discussed. These methods utilize the notion of compatible sets of permissible functions (CSPFs) of Transduction Method. Experimental results show the effectiveness of our methods.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130886140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信