{"title":"Multiprocessor Mapping of Process Networks: A JPEG Decoding Case Study","authors":"E. Kock","doi":"10.1109/ISSS.2002.1227154","DOIUrl":"https://doi.org/10.1109/ISSS.2002.1227154","url":null,"abstract":"We present a system-level design and programming method for embedded multiprocessor systems. The aim of the method is to improve the design time and design quality by providing a structured approach for implementing process networks. We use process networks as re-usable and architecture-independent functional specifications. The method facilitates the cost-driven and constraint-driven source code transformation of process networks into architecture-specific implementations in the form of communicating tasks. We apply the method to implement a JPEG decoding process network in software on a set of MIPS processors. We apply three transformations to optimize synchronization rates and data transfers and to exploit data parallelism for this target architecture. We evaluate the impact of the source code transformations and the performance of the resulting implementations in terms of design time, execution time, and code size. The results show that process networks can be implemented quickly and efficiently on embedded multiprocessor systems.","PeriodicalId":118601,"journal":{"name":"International Symposium on Systems Synthesis","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116873880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Formal Analysis of the iKP Electronic Payment Protocols","authors":"K. Ogata, K. Futatsugi","doi":"10.1007/3-540-36532-X_25","DOIUrl":"https://doi.org/10.1007/3-540-36532-X_25","url":null,"abstract":"","PeriodicalId":118601,"journal":{"name":"International Symposium on Systems Synthesis","volume":"172 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120941109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Jerraya, P. Paulin, R. Norman, Feliks J. Welfeld
{"title":"Programming models for network processors","authors":"A. Jerraya, P. Paulin, R. Norman, Feliks J. Welfeld","doi":"10.1145/500001.500049","DOIUrl":"https://doi.org/10.1145/500001.500049","url":null,"abstract":"","PeriodicalId":118601,"journal":{"name":"International Symposium on Systems Synthesis","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125814203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
W. Rosenstiel, B. Bailey, M. Fujita, G. Gao, Rajesh K. Gupta, P. Panda
{"title":"New design paradigms: what needs to be standardized?","authors":"W. Rosenstiel, B. Bailey, M. Fujita, G. Gao, Rajesh K. Gupta, P. Panda","doi":"10.1145/500001.500023","DOIUrl":"https://doi.org/10.1145/500001.500023","url":null,"abstract":"","PeriodicalId":118601,"journal":{"name":"International Symposium on Systems Synthesis","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115326232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Architectures for one billion of transistors","authors":"M. Valero","doi":"10.1145/501790.501805","DOIUrl":"https://doi.org/10.1145/501790.501805","url":null,"abstract":"Transistor budgets have been increasing at a very fast pace in the last years. This increasing transistor density will lead next generation processors to have a billion transistors available. It is the task of the computer architect to find the best way to use them.Out of order superscalar processors exploit parallelism at the finer grain, exploiting Instruction Level Parallelism (ILP). They issue multiple instructions per cycle, often in an order other than the specified by the programmer, using branch prediction and other speculative execution techniques in order to increase the available parallelism.Very Long Instruction Word (VLIW) processors also exploit parallelism at the instruction level, but they mostly rely on the compiler to detect the available parallelism. This increased compiler role allows a simpler design, and can be run at a faster clock rate, compensating for the loss of ILP.Chip Multiprocessors (CMP) join several narrow superscalar/VLIW components into a single processor, and mostly rely on the Thread Level Parallelism (TLP) for performance. The small and simple components can also run at a faster clock rate compensating for the loss of ILP, and significantly increasing throughput.Simultaneous Multithreaded (SMT) processors are based on wide superscalars, and exploit both ILP and TLP by issuing instructions from several different threads to the same pipeline, obtaining the benefits of TLP without sacrificing the ILP on single-threaded applications.For each of these options we will need to find the best balance between performance, design complexity, and power consumption among other factors. Also, the frontiers between them are not clear, and many intermediate design points can be found which leads to better/simpler/cheaper processors for the next generation of high performance computers.","PeriodicalId":118601,"journal":{"name":"International Symposium on Systems Synthesis","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126162543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Synthesis of low-power selectively-clocked systems from high-level specification","authors":"L. Benini, P. Vuillod, C. J. Coelho, G. Micheli","doi":"10.1145/348019.348050","DOIUrl":"https://doi.org/10.1145/348019.348050","url":null,"abstract":"In this paper we propose a technique for synthesizing low-power systems from a high-level specification. We analyze the control flow of the specification to detect mutually exclusive sections of the computation. A selectively-clocked interconnection of interacting FSMs is automatically generated and optimized where each FSM controls the execution of one section of computation. Only one of the interacting FSMs is active at any given clock cycle, while all the others are idle and their clock is stopped. Our interacting FSM implementation achieves consistently lower power dissipation savings are obtained with a 30% area overhead.","PeriodicalId":118601,"journal":{"name":"International Symposium on Systems Synthesis","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127657226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On the Rapid Prototyping and Design of a Wireless Communication System on a Chip","authors":"B. Kelley","doi":"10.1109/ICCAD.1999.810720","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810720","url":null,"abstract":"The evolutionary convergence of computing, integrated circuit technology, and advances in wireless communications has led to an explosive growth of personal communication devices and services (PCS). In fact, the dramatic \"Moore's Law\" shrinkage of IC devices, itself, has lead to an unprecedented ability to place increasingly complex systems on a chip (SoC).In a wireless communication environment, the integration task is made more difficult by the need to integrate RF, mixed signal, and digital systems. Furthermore, the digital system design task generally requires a mapping of heterogeneous stacks of software processes onto a similarly diverse collection of digital signal processors, microprocessors and application-specific integrated circuits.In this presentation, we give an overview of a modern wireless communication device and describe advanced system-level design methodologies utilized for rapid prototyping and design of current and next generation systems.","PeriodicalId":118601,"journal":{"name":"International Symposium on Systems Synthesis","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125280128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Breakpoints and Breakpoint Detection in Source Level Emulation","authors":"G. Koch, U. Kebschull, W. Rosenstiel","doi":"10.1145/290833.290843","DOIUrl":"https://doi.org/10.1145/290833.290843","url":null,"abstract":"In this paper we discuss, what breakpoints in Source Level Emulation are, how we can work with them and how we have to change the cicuit generated by high level synthesis to do so. We show the details of breakpoint encoding and detection in our approach. The presented approach allows for breakpoint detection by hardware means without seriously slowing down the circuit or dramatically increasing its size.","PeriodicalId":118601,"journal":{"name":"International Symposium on Systems Synthesis","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128246249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An Efficient ILP-Based Scheduling Algorithm for Control-Dominated VHDL Descriptions","authors":"M. Münch, M. Glesner, N. Wehn","doi":"10.1145/268424.268428","DOIUrl":"https://doi.org/10.1145/268424.268428","url":null,"abstract":"In this paper, we present for the first time a mathematical framework for solving a special instance of the scheduling problem in control-flow dominated behavioral VHDL descriptions given that the timing of I/O signals has been completely or partially specified. It is based on a code-transformational approach which fully preserves the VHDL semantics. The scheduling problem is mapped onto an integer linear program (ILP) which can be constrained to be solvable in polynomial time, but still permits optimizing the statement sequence across basic block boundaries.","PeriodicalId":118601,"journal":{"name":"International Symposium on Systems Synthesis","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134520082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Real-time systems specification and verification","authors":"J. Sifakis","doi":"10.1145/224486.224502","DOIUrl":"https://doi.org/10.1145/224486.224502","url":null,"abstract":"","PeriodicalId":118601,"journal":{"name":"International Symposium on Systems Synthesis","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122659171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}