2015 IEEE International Symposium on Multiple-Valued Logic最新文献_第3页

An RNS FFT Circuit Using LUT Cascades Based on a Modulo EVMDD 基于模EVMDD的LUT级联RNS FFT电路

2015 IEEE International Symposium on Multiple-Valued Logic Pub Date : 2015-05-18 DOI: 10.1109/ISMVL.2015.41

Hiroki Nakahara, Tsutomu Sasao, H. Nakanishi, K. Iwai

{"title":"An RNS FFT Circuit Using LUT Cascades Based on a Modulo EVMDD","authors":"Hiroki Nakahara, Tsutomu Sasao, H. Nakanishi, K. Iwai","doi":"10.1109/ISMVL.2015.41","DOIUrl":"https://doi.org/10.1109/ISMVL.2015.41","url":null,"abstract":"This paper proposes an FFT circuit based on a residue number system (RNS) using LUT cascades. To reduce the number of look-up tables (LUTs) in an FPGA, we used two techniques. The first one is the functional decomposition of multipliers using RNS. The second one is the increase of the dynamic range stage by stage. The circuit requires the RNS2RNS converter which converts a small dynamic range to a large dynamic range. To compactly realize the RNS2RNS converter, we decompose it into an RNS2Binary converter and a Binary2RNS converter. Although the Binary2RNS converter can be realized by an LUT cascade based on a multi-terminal multi-valued decision diagram (MTMDD), the RNS2Binary converter tend to be large for the conventional circuit. Thus, we introduce an LUT cascade based on a modulo edge-valued multi-valued decision diagram (mod-EVMDD). The mod-EVMDD is a new type of a decision diagram that efficiently represents the RNS2Binary converter. We implemented the proposed RNS FFT on the Xilinx Corp. Virtex 6 FPGA. Compared with the conventional binary FFT implementation, although the number of block RAMs (BRAMs) increased by 11.1-25.0%, the number of LUTs decreased by 44.2-52.2% and the maximum clock frequency increased by 9.3-41.7%. With this technique, we successfully implemented a required FFT on an available FPGA, since the excessive number of LUTs was the bottleneck of the binary FFT.","PeriodicalId":118417,"journal":{"name":"2015 IEEE International Symposium on Multiple-Valued Logic","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122752145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Novel VLSI Architectures for Real-World Intelligent Systems 面向现实世界智能系统的新型VLSI架构

2015 IEEE International Symposium on Multiple-Valued Logic Pub Date : 2015-05-18 DOI: 10.1109/ISMVL.2015.39

M. Kameyama

引用次数: 0

Non-Binary Analog-to-Digital Converter Based on Amoeba-Inspired Neural Network 基于阿米巴启发神经网络的非二进制模数转换器

2015 IEEE International Symposium on Multiple-Valued Logic Pub Date : 2015-05-18 DOI: 10.1109/ISMVL.2015.13

Uichi Ishida, Y. Yamazaki, T. Waho

引用次数: 2

A Reduction Method for the Number of Variables to Represent Index Generation Functions: s-Min Method 表示索引生成函数的变量数约简方法:s-Min法

2015 IEEE International Symposium on Multiple-Valued Logic Pub Date : 2015-05-18 DOI: 10.1109/ISMVL.2015.40

Tsutomu Sasao

引用次数: 21

Algebras and Algorithms 代数与算法

2015 IEEE International Symposium on Multiple-Valued Logic Pub Date : 2015-05-18 DOI: 10.1109/ISMVL.2015.45

M. Valeriote

引用次数: 0

Single-Electron Transistor Based Implementation of NOT, Feynman, and Toffoli Gates 基于非、费曼和托佛利门的单电子晶体管实现

2015 IEEE International Symposium on Multiple-Valued Logic Pub Date : 2015-05-18 DOI: 10.1109/ISMVL.2015.12

Mozammel H. A. Khan

{"title":"Single-Electron Transistor Based Implementation of NOT, Feynman, and Toffoli Gates","authors":"Mozammel H. A. Khan","doi":"10.1109/ISMVL.2015.12","DOIUrl":"https://doi.org/10.1109/ISMVL.2015.12","url":null,"abstract":"NOT, Feynman, and Toffoli gates are the practical building blocks of reversible circuit synthesis techniques. NOT and Feynman gates are primitive quantum gates. Toffoli gates are macro-level gates and realized using various primitive quantum gates. In reversible circuit design papers, logic level circuits are first realized using NOT, Feynman, and Toffoli gates and then the Toffoli gates are decomposed into primitive quantum gates. However, realizations of reversible circuits using electronic devices are not given adequate emphasis. In this paper, we propose preliminary ideas of implementations of NOT, Feynman, and Toffoli gates using single-electron transistor (SET), which is a nano-electronic quantum-tunneling device. NOT gate implementation requires one SET and one pull-up resistor. Feynman gate implementation requires two SETs and two pull-up resistors. Three-input Toffoli gate implementation requires three SETs and two pull-up resistors. The average static power consumptions of NOT, Feynman, and three-input Toffoli gate realizations are 0.091 nW, 0.497 nW, and 0.504 nW, respectively. The proposed implementations will open a facet of nano-electronic low-power realizations of reversible circuits.","PeriodicalId":118417,"journal":{"name":"2015 IEEE International Symposium on Multiple-Valued Logic","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133433065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Quotient Structures of Non-Commutative Residuated Lattices 非交换剩余格的商结构

2015 IEEE International Symposium on Multiple-Valued Logic Pub Date : 2015-05-18 DOI: 10.1109/ISMVL.2015.30

M. Kondo

引用次数: 0

Dynamic Template Matching with Mixed-Polarity Toffoli Gates 混合极性Toffoli门的动态模板匹配

2015 IEEE International Symposium on Multiple-Valued Logic Pub Date : 2015-05-18 DOI: 10.1109/ISMVL.2015.44

M. Rahman, Mathias Soeken, G. Dueck

引用次数: 4

Early-Stage Operation-Skipping Scheme for Low-Power Stochastic Image Processors 低功耗随机图像处理器的早期跳运算方案

2015 IEEE International Symposium on Multiple-Valued Logic Pub Date : 2015-05-18 DOI: 10.1109/ISMVL.2015.28

Daisaku Katagiri, N. Onizawa, T. Hanyu

引用次数: 0