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An automatic pulse alignment method for slope controlled super-regenerative receiver systems 斜坡控制超再生接收机系统的自动脉冲对准方法
2007 Ph.D Research in Microelectronics and Electronics Conference Pub Date : 2007-07-02 DOI: 10.1109/RME.2007.4401827
P. Thoppay, C. Dehollain, M. Declercq
{"title":"An automatic pulse alignment method for slope controlled super-regenerative receiver systems","authors":"P. Thoppay, C. Dehollain, M. Declercq","doi":"10.1109/RME.2007.4401827","DOIUrl":"https://doi.org/10.1109/RME.2007.4401827","url":null,"abstract":"Recently there is an increase in interest for using super-regenerative receivers for pulse based communication systems. To receive a pulse using the super-regenerative architecture the pulse needs to be aligned with the zero crossing of the damping co-efficient (which depends on the quench signal) for achieving maximum sensitivity. In general, the pulse to be received is not aligned with the zero crossing of the damping co-efficient. In this paper a novel technique for an automatic alignment of the incoming pulse with the zero crossing in a slope controlled super-regenerative system is proposed. The proof of concept is shown using MAT LAB simulations. Also a complete digital delay line architecture for delaying the quench signal which is a critical block in pulse alignment is described.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132112979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Efficient acquisition and analysis of digital signals in pin-limited system-on-package. 在引脚有限的系统级封装中有效地采集和分析数字信号。
2007 Ph.D Research in Microelectronics and Electronics Conference Pub Date : 2007-07-02 DOI: 10.1109/RME.2007.4401864
L. Mostardini, L. Benvenuti, L. Bacciarelli, L. Fanucci, C. Rosadini, A. Rocchi, M. De Marinis
{"title":"Efficient acquisition and analysis of digital signals in pin-limited system-on-package.","authors":"L. Mostardini, L. Benvenuti, L. Bacciarelli, L. Fanucci, C. Rosadini, A. Rocchi, M. De Marinis","doi":"10.1109/RME.2007.4401864","DOIUrl":"https://doi.org/10.1109/RME.2007.4401864","url":null,"abstract":"The paper presents an advanced digital signal inspector (ADSI) used for acquisition and analysis of the internal digital of a System on Package (SoP) with a limited number of pins. The system is made of a commercial FPGA- board, connected to the module for data sampling and controlled by PC via USB; a suited graphical interface allows for configuration, multi trace real time data display and post processing. The proposed platform can be used to extract and monitor simultaneously up to 4 digital signals, and an ADC is used to monitor one further analog signal. The ADSI has been successfully applied for the characterization of an automotive SoP based on a MEM gyro sensor interfaced to an ASIC for proper signal conditioning. The ADC was connected to an external accelerometer to evaluate the SoP behaviour when applying mechanical shocks.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"12 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114104558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The factorial Delay Locked Loop: a solution to fulfill multistandard RF synthesizer requirements 阶乘延迟锁环:满足多标准射频合成器要求的解决方案
2007 Ph.D Research in Microelectronics and Electronics Conference Pub Date : 2007-07-02 DOI: 10.1109/RME.2007.4401843
C. Majek, Y. Deval, H. Lapuyade, J. Bégueret
{"title":"The factorial Delay Locked Loop: a solution to fulfill multistandard RF synthesizer requirements","authors":"C. Majek, Y. Deval, H. Lapuyade, J. Bégueret","doi":"10.1109/RME.2007.4401843","DOIUrl":"https://doi.org/10.1109/RME.2007.4401843","url":null,"abstract":"This paper presents the study of a frequency synthesizer dedicated to multistandard wireless objects: the factorial delay locked loop (DLL). Feasibility of such a circuit has been already made, according to behavioral simulations, but no investigation was performed on the ability of the system to take into account all the requirements of multistandard frequency synthesizer, and particularly, the phase noise response of the system.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124694882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Calculation of sequence lengths in MASH 1-1-1 digital delta sigma modulators with a constant input 具有恒定输入的mast1.1 -1数字δ σ调制器序列长度的计算
2007 Ph.D Research in Microelectronics and Electronics Conference Pub Date : 2007-07-02 DOI: 10.1109/RME.2007.4401799
K. Hosseini, M. Kennedy, Cathal McCarthy
{"title":"Calculation of sequence lengths in MASH 1-1-1 digital delta sigma modulators with a constant input","authors":"K. Hosseini, M. Kennedy, Cathal McCarthy","doi":"10.1109/RME.2007.4401799","DOIUrl":"https://doi.org/10.1109/RME.2007.4401799","url":null,"abstract":"Knowledge of exact sequence lengths of undithered digital delta sigma modulators (DDSM) with respect to the input, initial conditions, and quantizer modulus, enables designers to predict spur intervals. It is necessary to know the sequence length for some applications such as fractional-N frequency synthesizers. In this paper, sequence lengths of multi stAge noise SHaping (MASH) DDSMs comprising first order error feedback modulators (EFM) up to three stages are calculated. Exact formulae for calculating sequence lengths with all possible inputs, initial conditions and moduli are provided for first and second order modulators. In the case of a third order modulator, the sequence length is found for the special case when it is not divisible by 3 but it is divisible by 4.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114965573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Analog circuit design at and below VT + 2Vds,sat VT + 2Vds及以下的模拟电路设计
2007 Ph.D Research in Microelectronics and Electronics Conference Pub Date : 2007-07-02 DOI: 10.1109/RME.2007.4401850
K. Layton, D. Comer, D. Comer
{"title":"Analog circuit design at and below VT + 2Vds,sat","authors":"K. Layton, D. Comer, D. Comer","doi":"10.1109/RME.2007.4401850","DOIUrl":"https://doi.org/10.1109/RME.2007.4401850","url":null,"abstract":"Design methods and architectures for high-performance analog circuitry which operates at supply voltages at and below VT + 2 Vds,sat are developed. A low voltage amplifier is designed using these methods. The amplifier, fabricated in an AMIS 0.5 mum CMOS process with 0.8 V p-channel threshold voltages, is shown to operate at supply voltages as low as 0.75 V with full rail-to-rail input and output operation. The amplifier shows 105 dB of open loop gain and GBW of 0.31 MHz while dissipating 11.5 muW from a 0.8 V supply. The design methods may be used with advanced CMOS processes to further reduce the required analog supply voltage.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"69 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127982100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Low voltage integrated astable multivibrator based on a single CCII 基于单CCII的低压集成不稳定多谐振荡器
2007 Ph.D Research in Microelectronics and Electronics Conference Pub Date : 2007-07-02 DOI: 10.1109/RME.2007.4401841
S. Del Re, A. De Marcellis, G. Ferri, V. Stornelli
{"title":"Low voltage integrated astable multivibrator based on a single CCII","authors":"S. Del Re, A. De Marcellis, G. Ferri, V. Stornelli","doi":"10.1109/RME.2007.4401841","DOIUrl":"https://doi.org/10.1109/RME.2007.4401841","url":null,"abstract":"In this paper we present a new low voltage (1.5V supply) astable multivibrator, implemented with a single CCII , that performs a controlled square wave generation. Complete theory calculations are addressed. Simulation results, obtained by means of Cadence simulator, are in a good agreement with theoretical expectations. Since the CCII has been implemented at transistor level, in a standard CMOS technology, the proposed multivibrator can be completely integrated. The maximum oscillation frequency obtained from simulations is about 50 MHz.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128813452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
A full custom front-end ASIC prototype “CMAD” for COMPASS-RICH-1 particle detector system 一个完整的定制前端ASIC原型“CMAD”的指南针- rich -1粒子探测器系统
2007 Ph.D Research in Microelectronics and Electronics Conference Pub Date : 2007-07-02 DOI: 10.1109/RME.2007.4401822
O. Cobanoglu, M. Chiosso, P. Delaurenti, G. Mazza, D. Panzieri, A. Rivetti
{"title":"A full custom front-end ASIC prototype “CMAD” for COMPASS-RICH-1 particle detector system","authors":"O. Cobanoglu, M. Chiosso, P. Delaurenti, G. Mazza, D. Panzieri, A. Rivetti","doi":"10.1109/RME.2007.4401822","DOIUrl":"https://doi.org/10.1109/RME.2007.4401822","url":null,"abstract":"An 8 channel, full-custom ASIC prototype, named \"CMAD\", designed for the readout of the RICH-I detector system of the COMPASS experiment at CERN is presented. The task of the chip is amplifying the signals coming from fast multianode photomultipliers and comparing them against a threshold adjustable on-chip on a channel by channel basis. CMAD, developed using a 350 nm commercial CMOS technology, occupies an area of 4.7 x 3.2 mm2 and consumes 26 mW/Ch power from a 3.3 V single source.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116827436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A dynamically reconfigurable system-on-chip for implementing wireless MACs 用于实现无线mac的动态可重构片上系统
2007 Ph.D Research in Microelectronics and Electronics Conference Pub Date : 2007-07-02 DOI: 10.1109/RME.2007.4401805
S. Nabi, C. C. Wells, W. Vanderbauwhede
{"title":"A dynamically reconfigurable system-on-chip for implementing wireless MACs","authors":"S. Nabi, C. C. Wells, W. Vanderbauwhede","doi":"10.1109/RME.2007.4401805","DOIUrl":"https://doi.org/10.1109/RME.2007.4401805","url":null,"abstract":"This paper presents the architecture of a dynamically reconfigurable platform being developed specially for implementing wireless protocols' MAC layer for consumer wireless devices. The cornerstone of this architecture is the exploitation of substantial overlaps in the functionality of the three MACs considered. By using function-specific reconfigurable functional units that are based on the overlaps in the MAC functionality, and by using a heterogeneous architecture with restricted flexibility, we have argued that the architecture we have presented will give substantial power-savings over an equivalent FPGA or software implementation.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133197281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A low-power 6.3 GHz FBAR overtone-based oscillator in 90 nm CMOS technology 基于90nm CMOS技术的低功耗6.3 GHz FBAR泛音振荡器
2007 Ph.D Research in Microelectronics and Electronics Conference Pub Date : 2007-07-02 DOI: 10.1109/RME.2007.4401811
M. Elbarkouky, P. Wambacq, Y. Rolain
{"title":"A low-power 6.3 GHz FBAR overtone-based oscillator in 90 nm CMOS technology","authors":"M. Elbarkouky, P. Wambacq, Y. Rolain","doi":"10.1109/RME.2007.4401811","DOIUrl":"https://doi.org/10.1109/RME.2007.4401811","url":null,"abstract":"Film bulk acoustic wave resonators (FBARs) are useful to make very selective filters and low-power oscillators in the low-GHz frequency region. To extend the useful range of FBARs to higher frequencies, we demonstrate the use of an FBAR at an overtone frequency. A Colpitts oscillator has been designed by combining via wire bonding 90 nm CMOS circuitry with an FBAR on a separate chip. The simulated oscillation frequency of the oscillator is 6.3 GHz with a power consumption of 475 muW in the core. The oscillator achieves phase noise of-110 dBc/Hz at 1 MHz offset from the carrier. To the authors' knowledge this is the first FBAR overtone- based oscillator in the low-GHz range.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133513471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Low level and high linearity amplifiers in integrated technologies for satellite receivers: Technical issues of linearization techniques 卫星接收机集成技术中的低电平和高线性放大器:线性化技术的技术问题
2007 Ph.D Research in Microelectronics and Electronics Conference Pub Date : 2007-07-02 DOI: 10.1109/RME.2007.4401834
J. Tapfuh-Mouafo, B. Jarry, M. Campovechio, J. Villemazet, J. Cazaux
{"title":"Low level and high linearity amplifiers in integrated technologies for satellite receivers: Technical issues of linearization techniques","authors":"J. Tapfuh-Mouafo, B. Jarry, M. Campovechio, J. Villemazet, J. Cazaux","doi":"10.1109/RME.2007.4401834","DOIUrl":"https://doi.org/10.1109/RME.2007.4401834","url":null,"abstract":"Based on carrier to third intermodulation ratio (C/I3), reverse engineering of a two stages low level amplifier has been made in order to access the current transistor nonlinear models. Comparisons between two models of HEMT have been performed in order to choose the one which represent accurately weak nonlinearities at low level power dynamic range. By judicious choice of bias point, 12 dB improvement of linearity has been achieved. Other issues of linearization techniques have been studied so that to be suitable for MMIC implementation.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133272715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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