阶乘延迟锁环:满足多标准射频合成器要求的解决方案

2007 Ph.D Research in Microelectronics and Electronics Conference Pub Date : 2007-07-02 DOI:10.1109/RME.2007.4401843

C. Majek, Y. Deval, H. Lapuyade, J. Bégueret

{"title":"阶乘延迟锁环:满足多标准射频合成器要求的解决方案","authors":"C. Majek, Y. Deval, H. Lapuyade, J. Bégueret","doi":"10.1109/RME.2007.4401843","DOIUrl":null,"url":null,"abstract":"This paper presents the study of a frequency synthesizer dedicated to multistandard wireless objects: the factorial delay locked loop (DLL). Feasibility of such a circuit has been already made, according to behavioral simulations, but no investigation was performed on the ability of the system to take into account all the requirements of multistandard frequency synthesizer, and particularly, the phase noise response of the system.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"The factorial Delay Locked Loop: a solution to fulfill multistandard RF synthesizer requirements\",\"authors\":\"C. Majek, Y. Deval, H. Lapuyade, J. Bégueret\",\"doi\":\"10.1109/RME.2007.4401843\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the study of a frequency synthesizer dedicated to multistandard wireless objects: the factorial delay locked loop (DLL). Feasibility of such a circuit has been already made, according to behavioral simulations, but no investigation was performed on the ability of the system to take into account all the requirements of multistandard frequency synthesizer, and particularly, the phase noise response of the system.\",\"PeriodicalId\":118230,\"journal\":{\"name\":\"2007 Ph.D Research in Microelectronics and Electronics Conference\",\"volume\":\"24 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-07-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 Ph.D Research in Microelectronics and Electronics Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RME.2007.4401843\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 Ph.D Research in Microelectronics and Electronics Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RME.2007.4401843","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 10

摘要

本文研究了一种专用于多标准无线对象的频率合成器:阶乘延迟锁环(DLL)。根据行为模拟，这种电路的可行性已经得到证实，但没有对系统考虑多标准频率合成器的所有要求，特别是系统的相位噪声响应的能力进行调查。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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The factorial Delay Locked Loop: a solution to fulfill multistandard RF synthesizer requirements

This paper presents the study of a frequency synthesizer dedicated to multistandard wireless objects: the factorial delay locked loop (DLL). Feasibility of such a circuit has been already made, according to behavioral simulations, but no investigation was performed on the ability of the system to take into account all the requirements of multistandard frequency synthesizer, and particularly, the phase noise response of the system.

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2007 Ph.D Research in Microelectronics and Electronics Conference

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