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Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005.最新文献

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Experimental validation of a new analytical model for the position-dependent Hall voltage in semiconductor devices 半导体器件中位置相关霍尔电压新分析模型的实验验证
Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005. Pub Date : 2005-12-12 DOI: 10.1109/ESSDER.2005.1546711
M. Rudan, S. Reggiani, E. Gnani, G. Baccarani, C. Corvasce, D. Barlini, M. Ciappa, W. Fichtner, M. Denison, N. Jensen, G. Groos, M. Stecher
{"title":"Experimental validation of a new analytical model for the position-dependent Hall voltage in semiconductor devices","authors":"M. Rudan, S. Reggiani, E. Gnani, G. Baccarani, C. Corvasce, D. Barlini, M. Ciappa, W. Fichtner, M. Denison, N. Jensen, G. Groos, M. Stecher","doi":"10.1109/ESSDER.2005.1546711","DOIUrl":"https://doi.org/10.1109/ESSDER.2005.1546711","url":null,"abstract":"A number of devices, that are under investigation for implementing and calibrating physical models at high operating temperatures and transient high current stress, exhibit geometrical features that do not allow for the application of the elementary Hall theory. This makes the outcome of measurements based on the Hall effect unreliable. A more general theory has been developed, that leads to the determination of the Hall voltage as a function of the position along the longitudinal direction of the device channel. Devices with several pairs of Hall probes have been designed and manufactured, and the Hall voltage along their sides has carefully been measured. The experimental results led to a thorough validation of the theory.","PeriodicalId":117719,"journal":{"name":"Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005.","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115211156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The role of nitrogen incorporation in Hf-based high-k dielectrics: reduction in electron charge traps 氮掺入在hf基高k介电体中的作用:电子电荷阱的还原
Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005. Pub Date : 2005-12-12 DOI: 10.1109/ESSDER.2005.1546620
N. Umezawa, K. Shiraishi, K. Torii, M. Boero, T. Chikyow, H. Watanabe, K. Yamabe, T. Ohno, K. Yamada, Y. Nara
{"title":"The role of nitrogen incorporation in Hf-based high-k dielectrics: reduction in electron charge traps","authors":"N. Umezawa, K. Shiraishi, K. Torii, M. Boero, T. Chikyow, H. Watanabe, K. Yamabe, T. Ohno, K. Yamada, Y. Nara","doi":"10.1109/ESSDER.2005.1546620","DOIUrl":"https://doi.org/10.1109/ESSDER.2005.1546620","url":null,"abstract":"The N incorporation effect in Hf-based high-k gate dielectrics has been studied by the first-principles calculations. Interactions between N atoms and oxygen vacancies (Vos) in HfO/sub 2/ are investigated. Our calculations show that N atoms favorably occupy nearest neighbor oxygen sites to Vos. As a result, electron charge traps at Vos are remarkably suppressed due to the strong repulsive Coulomb interactions between electrons and negatively charged N/sup 3-/ ions. These results indicate that N incorporation improves positive bias temperature instability (PBTI) in Hf related high-k gate stacks. Moreover, our calculations have also revealed that the Vo formation energy is remarkably reduced by N incorporation.","PeriodicalId":117719,"journal":{"name":"Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124468816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Silicidation induced strain phenomena in totally silicided (TOSI) gate transistors 全硅化栅极晶体管中硅化引起的应变现象
Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005. Pub Date : 2005-12-12 DOI: 10.1109/ESSDER.2005.1546676
A. Mondot, M. Muller, D. Aimé, B. Froment, F. Cacho, A. Talbot, F. Leverd, M. Rivoire, Y. Morand, S. Descombes, P. Besson, A. Toffoli, S. Pokrant, T. Skotnicki
{"title":"Silicidation induced strain phenomena in totally silicided (TOSI) gate transistors","authors":"A. Mondot, M. Muller, D. Aimé, B. Froment, F. Cacho, A. Talbot, F. Leverd, M. Rivoire, Y. Morand, S. Descombes, P. Besson, A. Toffoli, S. Pokrant, T. Skotnicki","doi":"10.1109/ESSDER.2005.1546676","DOIUrl":"https://doi.org/10.1109/ESSDER.2005.1546676","url":null,"abstract":"In this paper, we present a detailed analysis of the performance and transport characteristics in totally Ni silicided (TOSI) devices. For two different TOSI integration schemes, we study transconductance variations of TOSI devices with respect to poly-Si gated devices. We find a clear signature of process induced strain related to the total gate silicidation step which depends largely on the integration scheme used for the fabrication of the TOSI devices.","PeriodicalId":117719,"journal":{"name":"Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005.","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116642854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Finite element simulation of thermomechanical stress evolution in Cu/low-k interconnects during manufacturing and subsequent thermal cycling Cu/low-k互连在制造和后续热循环过程中热-机械应力演化的有限元模拟
Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005. Pub Date : 2005-12-12 DOI: 10.1109/ESSDER.2005.1546692
N. Cherault, J. Besson, C. Goldberg, N. Casanova, M. Berger
{"title":"Finite element simulation of thermomechanical stress evolution in Cu/low-k interconnects during manufacturing and subsequent thermal cycling","authors":"N. Cherault, J. Besson, C. Goldberg, N. Casanova, M. Berger","doi":"10.1109/ESSDER.2005.1546692","DOIUrl":"https://doi.org/10.1109/ESSDER.2005.1546692","url":null,"abstract":"The integration of low-k interlayer dielectrics in interconnects is associated with an increase in mechanical reliability risks. Thermomechanical stresses must be evaluated to understand the behavior of interconnects. As manufacturing processes can introduce large stresses, a sequential process modeling technique is developed in this study. The constituent materials of the interconnects are described by a single elasto-plastic constitutive equation developed from substrate curvature measurements. Stresses in Cu/low-k lines are also evaluated. A good correlation between finite element modeling and curvature measurements is obtained.","PeriodicalId":117719,"journal":{"name":"Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005.","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116875396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Integration of substrate-isolated high voltage devices in junction isolated technologies 结隔离技术中基板隔离高压器件的集成
Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005. Pub Date : 2005-12-12 DOI: 10.1109/ESSDER.2005.1546690
S. Pendharkar
{"title":"Integration of substrate-isolated high voltage devices in junction isolated technologies","authors":"S. Pendharkar","doi":"10.1109/ESSDER.2005.1546690","DOIUrl":"https://doi.org/10.1109/ESSDER.2005.1546690","url":null,"abstract":"This paper discusses how the voltage capability of the existing junction isolation (JI) based smart power bipolar-CMOS-DMOS (BCD) technologies for a 12V electrical automotive systems can be easily up-converted to support the new 42V electrical automotive systems. The modular integration and the new high voltage device architecture used to achieve this are also discussed in this paper.","PeriodicalId":117719,"journal":{"name":"Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005.","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116042629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Minimization of the MuGFET contact resistance by integration of NiSi contacts on epitaxially raised source/drain regions 通过在外延凸起的源极/漏极区域集成NiSi触点来最小化MuGFET接触电阻
Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005. Pub Date : 2005-12-12 DOI: 10.1109/ESSDER.2005.1546680
A. Dixit, K. Anil, R. Rooyackers, M. Kaiser, R. Weemaes, I. Ferain, A. De Keersgieter, N. Collaert, R. Surdeanu, M. Goodwin, P. Zimmerman, R. Loo, M. Caymax, M. Jurczak, S. Biesemans, K. De Meyer, F. Leys
{"title":"Minimization of the MuGFET contact resistance by integration of NiSi contacts on epitaxially raised source/drain regions","authors":"A. Dixit, K. Anil, R. Rooyackers, M. Kaiser, R. Weemaes, I. Ferain, A. De Keersgieter, N. Collaert, R. Surdeanu, M. Goodwin, P. Zimmerman, R. Loo, M. Caymax, M. Jurczak, S. Biesemans, K. De Meyer, F. Leys","doi":"10.1109/ESSDER.2005.1546680","DOIUrl":"https://doi.org/10.1109/ESSDER.2005.1546680","url":null,"abstract":"High parasitic S/D resistance is a major obstacle in realizing future generations of CMOS technologies using multiple gate devices with narrow fins. This makes selective epitaxial growth of Si in the S/D regions, the enabling process for multiple gate CMOS technologies. In this paper, we endeavor to integrate a low temperature selective epitaxial growth process and a low temperature NiSi process to form low resistance S/D contacts. Our experimental results show 34% and 11% improvement in parasitic S/D resistance of N-and P-channel multiple gate FETs with less than 20 nm wide fins respectively.","PeriodicalId":117719,"journal":{"name":"Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116449221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Do hot electrons produce excess noise? 热电子会产生多余的噪音吗?
Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005. Pub Date : 2005-12-12 DOI: 10.1109/ESSDER.2005.1546652
C. Jungemann, B. Meinerzhagen
{"title":"Do hot electrons produce excess noise?","authors":"C. Jungemann, B. Meinerzhagen","doi":"10.1109/ESSDER.2005.1546652","DOIUrl":"https://doi.org/10.1109/ESSDER.2005.1546652","url":null,"abstract":"The open question whether excess noise is due to hot electrons or not is addressed for the first time by solving the Langevin Boltzmann equation. Not only is the bulk case analyzed but also devices. In contrast to the well-known Monte Carlo method this new approach allows the investigation of the spatial origin of the terminal current noise. It is shown, that excess noise is mainly due to cold or warm electrons, whereas the contribution of hot electrons in a velocity-saturation region is negligible.","PeriodicalId":117719,"journal":{"name":"Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005.","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114571005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Effect of hot carrier stress on the performance, trap densities and transient behavior of SLS ELA TFTs 热载流子应力对SLS ELA TFTs性能、陷阱密度和瞬态行为的影响
Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005. Pub Date : 2005-12-12 DOI: 10.1109/ESSDER.2005.1546668
D. Kouvatsos, G. Papaioannou, M. Exarchos, L. Michalas, A. Voutsas
{"title":"Effect of hot carrier stress on the performance, trap densities and transient behavior of SLS ELA TFTs","authors":"D. Kouvatsos, G. Papaioannou, M. Exarchos, L. Michalas, A. Voutsas","doi":"10.1109/ESSDER.2005.1546668","DOIUrl":"https://doi.org/10.1109/ESSDER.2005.1546668","url":null,"abstract":"The effects of DC hot carrier stressing on the device parameters, the active layer trap densities and the carrier generation-trapping characteristics, as deduced from the transient drain current, for thin film transistors fabricated in polysilicon films crystallized using the advanced SLS ELA process are investigated. Both the total grain boundary trap density and the midgap trap density are found to degrade faster for TFTs in thicker films, with devices in ultra-thin films showing almost no trap generation. The application of HCS significantly affected the drain current transients, indicating the introduction of additional defects in the active layer that affect the carrier recombination process.","PeriodicalId":117719,"journal":{"name":"Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005.","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116587437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
High-speed InP-based resonant tunneling diode on silicon substrate 硅衬底高速inp谐振隧道二极管
Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005. Pub Date : 2005-12-12 DOI: 10.1109/ESSDER.2005.1546634
W. Prost, V. Khorenko, A. Mofor, A. Bakin, E. Khorenko, S. Ehrich, H. Wehmann, A. Schlachetzki, F. Tegude
{"title":"High-speed InP-based resonant tunneling diode on silicon substrate","authors":"W. Prost, V. Khorenko, A. Mofor, A. Bakin, E. Khorenko, S. Ehrich, H. Wehmann, A. Schlachetzki, F. Tegude","doi":"10.1109/ESSDER.2005.1546634","DOIUrl":"https://doi.org/10.1109/ESSDER.2005.1546634","url":null,"abstract":"A technology for high speed and high performance III-V semiconductor devices on silicon substrate has been developed. It consists of an InP-on-Si quasi-substrate exhibiting an XRD FWHM as low as 86 arcsec, followed by a low-temperature (370/spl deg/C) grown InAlAs layer. The surface roughness is reduced to 1.9 nm along with an almost complete elimination of surface defects. The applicability is experimentally verified for InP-based resonant tunneling diodes exhibiting a speed index of 32 ps/V indicating a potentially low-cost technology for high functionality circuits operating above 10 Gb/s.","PeriodicalId":117719,"journal":{"name":"Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005.","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128408621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
In-depth study of strained SGOI nMOSFETs down to 30nm gate length 深入研究了栅长为30nm的应变SGOI nmosfet
Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005. Pub Date : 2005-12-12 DOI: 10.1109/ESSDER.2005.1546644
F. Andrieu, T. Ernst, O. Faynot, O. Rozeau, Y. Bogumilowicz, J. Hartmann, L. Brevard, A. Toffoli, D. Lafond, H. Dansas, B. Ghyselen, F. Fournel, G. Ghibaudo, S. Deleonibus
{"title":"In-depth study of strained SGOI nMOSFETs down to 30nm gate length","authors":"F. Andrieu, T. Ernst, O. Faynot, O. Rozeau, Y. Bogumilowicz, J. Hartmann, L. Brevard, A. Toffoli, D. Lafond, H. Dansas, B. Ghyselen, F. Fournel, G. Ghibaudo, S. Deleonibus","doi":"10.1109/ESSDER.2005.1546644","DOIUrl":"https://doi.org/10.1109/ESSDER.2005.1546644","url":null,"abstract":"Partially depleted floating body transistors on SGOI down to 30nm gate length were fabricated and characterized. They demonstrate excellent static and RF performances. In particular, SGOI 40nm transistors exhibit at V/sub D/=1V a 840/spl mu/A//spl mu/m I/sub ON/ at 0.8V gate voltage overdrive (V/sub GT/) vs. 20/spl mu/A//spl mu/m I/sub OFF/ at V/sub GT/ = -0.2V and a maximum oscillation frequency (f/sub max/) estimated to be 150 GHz at V/sub G/=0.4V. The SGOI originality concerning the floating body effects and the short channel transport were studied in-depth to evaluate this architecture potentiality.","PeriodicalId":117719,"journal":{"name":"Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005.","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128689287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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