{"title":"Services and architectures for electronic publishing","authors":"David M. Choy, R. Morris","doi":"10.1109/CMPCON.1996.501785","DOIUrl":"https://doi.org/10.1109/CMPCON.1996.501785","url":null,"abstract":"We describe changes that are occurring in electronic publishing as a result of the emergence of networked computing. Networks facilitate the exchange of information, but the changes will be far more profound than a simple substitution of media. As new capabilities and new challenges arise, there are corresponding new services that must be developed or else electronic publishing will not meet the needs of the public. After discussing these services, we describe architectures that call be used to implement them. These architectures respond to the issues of performance, scalability, security, and economics that must be addressed before electronic publishing will blossom. We illustrate how current architectures support existing services, enhancements offered by multi-tier servers, and extensions of these architectures to more symmetric models such as the broker model. Many of these concepts are being pursued by the IBM Digital Library family of products.","PeriodicalId":117038,"journal":{"name":"COMPCON '96. Technologies for the Information Superhighway Digest of Papers","volume":"10 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128652392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A scalable chip set for MPEG2 real-time encoding","authors":"Agnes Y. Ngai","doi":"10.1109/CMPCON.1996.501768","DOIUrl":"https://doi.org/10.1109/CMPCON.1996.501768","url":null,"abstract":"This is a description of an architecture for video compression based on the MPEG2 (MP@ML) standard. The chip set is comprised of 3 different devices. The architecture is scalable, and real-time MPEG2 systems could be built with one, two or all three chip solutions. The encoder includes an on-chip processor for programming options, and provides direct connections to external DRAM and SRAM.","PeriodicalId":117038,"journal":{"name":"COMPCON '96. Technologies for the Information Superhighway Digest of Papers","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116642108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Interactive television settop terminal architectures","authors":"Ajith N. Nair","doi":"10.1109/CMPCON.1996.501774","DOIUrl":"https://doi.org/10.1109/CMPCON.1996.501774","url":null,"abstract":"Emerging architectures for Interactive TeleVision (ITV) Settop Terminals (ISTT) are discussed. The differences in the architectures for different delivery mechanisms has impact on cost and complexity of the STTs. The combinations of features required in the STTs and the level of silicon integration sometimes drive the architectures. The state of technology of building blocks required for implementing these STTs and future trends in silicon integration are discussed.","PeriodicalId":117038,"journal":{"name":"COMPCON '96. Technologies for the Information Superhighway Digest of Papers","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128300676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Structured workflow management with Lotus Notes Release 4","authors":"B. Reinwald, C. Mohan","doi":"10.1109/CMPCON.1996.501810","DOIUrl":"https://doi.org/10.1109/CMPCON.1996.501810","url":null,"abstract":"In this paper we describe the design and implementation of workflow management applications on top of Notes Release 4. We elaborate on various design issues for Notes workflow applications and introduce Notes Release 4's native workflow concepts like agents, events, macros, Lotus-Script, OLE2 capabilities, and doclinks, which make Notes a powerful workflow tool. The idea of the paper is the use of the Workflow Reference Model of the Workflow Management Coalition to define structured workflows, and execute these workflows through the exploitation of Notes Release 4's native workflow concepts.","PeriodicalId":117038,"journal":{"name":"COMPCON '96. Technologies for the Information Superhighway Digest of Papers","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115056486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Henne, Hal Hickel, Ewan Johnson, Sonoko Konishi
{"title":"The making of Toy Story [computer animation]","authors":"M. Henne, Hal Hickel, Ewan Johnson, Sonoko Konishi","doi":"10.1109/CMPCON.1996.501812","DOIUrl":"https://doi.org/10.1109/CMPCON.1996.501812","url":null,"abstract":"Toy Story is the first full length feature film produced entirely using the technology of computer animation. The main characters, Sheriff Woody and Space Ranger Buzz Lightyear; are toys that come to life when humans aren't around. Their story is one of rivalry, challenges, teamwork and redemption. Making this film required four years of effort, from writing the story and script, to illustrated storyboards, through modeling, animation, lighting, rendering, and filming. This paper examines various processes involved in producing the film.","PeriodicalId":117038,"journal":{"name":"COMPCON '96. Technologies for the Information Superhighway Digest of Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129488080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Multiprocessor validation of the Pentium Pro microprocessor","authors":"D. Marr, S. Thakkar, R. Zucker","doi":"10.1109/CMPCON.1996.501801","DOIUrl":"https://doi.org/10.1109/CMPCON.1996.501801","url":null,"abstract":"The Pentium Pro microprocessor, the latest generation Intel Architecture processor, was designed to be used glue-lessly in multiprocessor (MP) systems. The processor and its associated chipset provide all the features that an MP system requires. Our challenge was to ensure that the Pentium Pro would be MP functional with the expected performance at first silicon. We accomplished this by developing a test methodology with self-checking test templates for validating the processor's MP features, and using micro-benchmarks and high-level system models to verify MP hardware scalability.","PeriodicalId":117038,"journal":{"name":"COMPCON '96. Technologies for the Information Superhighway Digest of Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120985844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Architecture of a broadband mediaprocessor","authors":"Craig Hansen","doi":"10.1109/CMPCON.1996.501792","DOIUrl":"https://doi.org/10.1109/CMPCON.1996.501792","url":null,"abstract":"A broadband mediaprocessor is a general-purpose computer system which reaches the goal of communicating and processing at broadband rates using compiled software rather than special-purpose hardware. MicroUnity's architectural family of broadband mediaprocessors reduce costs of broadband communications systems and enable deployment of new communications services by transmitting software through digital networks.","PeriodicalId":117038,"journal":{"name":"COMPCON '96. Technologies for the Information Superhighway Digest of Papers","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123051575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"SSA: a high-performance serial interface for unparalleled connectivity","authors":"Andrew Wilson","doi":"10.1109/CMPCON.1996.501782","DOIUrl":"https://doi.org/10.1109/CMPCON.1996.501782","url":null,"abstract":"Serial Storage Architecture (SSA) is a new I/O interconnect which provides high levels of connectivity availability, performance and fault tolerance-all implemented with cost effective serial technology. The currently available dual port devices allow construction of simple loops with up to 128 nodes, and aggregate bandwidth of up to 80 MBytes per second. Future availability of switches and higher speed links will support thousands of nodes and much higher aggregate data rates.","PeriodicalId":117038,"journal":{"name":"COMPCON '96. Technologies for the Information Superhighway Digest of Papers","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122641973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"ARM7100-a high-integration, low-power microcontroller for PDA applications","authors":"G. Budd, G. Milne","doi":"10.1109/CMPCON.1996.501766","DOIUrl":"https://doi.org/10.1109/CMPCON.1996.501766","url":null,"abstract":"The ARM7100 is the first of a new generation of highly integrated ARM-based microcontrollers, using modular design techniques based on the Advanced Microcontroller Bus Architecture (AMBA) to simplify design and test while optimizing for lowest power (70 mW) and low die size. The ARM7100, which is targeted at PDA applications, delivers 18.4 MIPS (peak) at 3.3 V and contains an embedded ARM7l0a core (including 8 kByte cache and MMU) with ARM-library peripherals such as an LCD controller, UART and CODEC interface. This paper gives an overview of the ARM7100 microcontroller and describes the architecture used to optimize for low power while maintaining high performance.","PeriodicalId":117038,"journal":{"name":"COMPCON '96. Technologies for the Information Superhighway Digest of Papers","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121604977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Dynamic bandwidth allocation for interactive video applications over corporate networks","authors":"Carl J. Beckmann","doi":"10.1109/CMPCON.1996.501772","DOIUrl":"https://doi.org/10.1109/CMPCON.1996.501772","url":null,"abstract":"This paper discusses dynamic bandwidth management in corporate networks for supporting interactive multimedia applications. We show that particular characteristics of corporate networks and the highly dynamic resource requirements of interactive applications make dynamic allocation of network bandwidth both attractive and feasible. We compare several bandwidth allocation strategies via simulations based on the measured characteristic of an actual interactive TV application used in medical training.","PeriodicalId":117038,"journal":{"name":"COMPCON '96. Technologies for the Information Superhighway Digest of Papers","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133616868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}