{"title":"Multiprocessor validation of the Pentium Pro microprocessor","authors":"D. Marr, S. Thakkar, R. Zucker","doi":"10.1109/CMPCON.1996.501801","DOIUrl":null,"url":null,"abstract":"The Pentium Pro microprocessor, the latest generation Intel Architecture processor, was designed to be used glue-lessly in multiprocessor (MP) systems. The processor and its associated chipset provide all the features that an MP system requires. Our challenge was to ensure that the Pentium Pro would be MP functional with the expected performance at first silicon. We accomplished this by developing a test methodology with self-checking test templates for validating the processor's MP features, and using micro-benchmarks and high-level system models to verify MP hardware scalability.","PeriodicalId":117038,"journal":{"name":"COMPCON '96. Technologies for the Information Superhighway Digest of Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"COMPCON '96. Technologies for the Information Superhighway Digest of Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CMPCON.1996.501801","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
The Pentium Pro microprocessor, the latest generation Intel Architecture processor, was designed to be used glue-lessly in multiprocessor (MP) systems. The processor and its associated chipset provide all the features that an MP system requires. Our challenge was to ensure that the Pentium Pro would be MP functional with the expected performance at first silicon. We accomplished this by developing a test methodology with self-checking test templates for validating the processor's MP features, and using micro-benchmarks and high-level system models to verify MP hardware scalability.