2017 29th International Conference on Microelectronics (ICM)最新文献_第6页

An FPGA based DPLL with fuzzy logic controllable loop filters 基于FPGA的模糊逻辑可控环滤波器的DPLL

2017 29th International Conference on Microelectronics (ICM) Pub Date : 2017-12-01 DOI: 10.1109/ICM.2017.8268812

M. Moradi, M. Ehsanian

引用次数: 0

A ultra high speed and configurable Inverse Discrete Wavelet Packet Transform architecture 一个超高速和可配置的逆离散小波包变换体系结构

2017 29th International Conference on Microelectronics (ICM) Pub Date : 2017-12-01 DOI: 10.1109/ICM.2017.8268863

Mouhamad Chehaitly, M. Tabaa, F. Monteiro, A. Dandache

{"title":"A ultra high speed and configurable Inverse Discrete Wavelet Packet Transform architecture","authors":"Mouhamad Chehaitly, M. Tabaa, F. Monteiro, A. Dandache","doi":"10.1109/ICM.2017.8268863","DOIUrl":"https://doi.org/10.1109/ICM.2017.8268863","url":null,"abstract":"This article presents a new pipeline-parallel architecture of Inverse Discrete Wavelet Packet Transform (IDWPT) for all wavelet family implemented in FPGA technology using a parallel direct FIR filter. Our aim in this work is to develop a generic VHDL-RTL model and configurable architecture of pipeline-parallel architecture of IDWPT. This architecture provide ultra-high speed sample processing with a restricted amount of used hardware. To achieve that, we propose a P-parallel IDWPT based on Mallat binary tree algorithm and a P-parallel/modified direct FIR filter under the strategy of pipeline-parallel and sharing hardware resource. The key of this model is the data manage/interleaving of pipeline/P-parallel concept and shared hardware of different level in the transformation. This architecture is fully configurable: (i) in synthesis according of various parameters like the parallel degree, the tree depth (number of tree levels), the order of the filters and the filter quantization coefficient and (ii) in pro-synthesis according to the coefficients of low-pass and high-pass filters, in other words the filters coefficients can be loaded after synthesis. Consequently, the simulation results accelerated to an approximate value of P∗(Frequency). Furthermore, the tree depth and filters order has little impact (only due to place and route variations) on throughput. This architecture was synthesized using Altera Quartus prime lite edition targeting an Altera Cyclone IV — (FPGA) and it was developed in VHDL at RTL level modeling.","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128575830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Implementation of a bidirecional serial communication protocol using shared channel 利用共享信道实现双向串行通信协议

2017 29th International Conference on Microelectronics (ICM) Pub Date : 2017-12-01 DOI: 10.1109/ICM.2017.8268889

A. Rodrigues, R. Moreno, P. Crepaldi, T. Pimenta

引用次数: 1

An ultra low-power digital to analog converter for SAR ADCs 一种用于SAR adc的超低功耗数模转换器

2017 29th International Conference on Microelectronics (ICM) Pub Date : 2017-12-01 DOI: 10.1109/ICM.2017.8268844

Ata Khorami, M. Sharifkhani

引用次数: 1

Calibration of SAR analog-to-digital converters for expanding the sampling rate range 校正SAR模数转换器以扩大采样率范围

2017 29th International Conference on Microelectronics (ICM) Pub Date : 2017-12-01 DOI: 10.1109/ICM.2017.8268865

Abbas Naghibzadeh, H. Rezaee-Dehsorkh, N. Ravanshad

引用次数: 0

Localization of a VHF transmitter based on PDOA methods: Simulations and experiments 基于PDOA方法的甚高频发射机定位:仿真与实验

2017 29th International Conference on Microelectronics (ICM) Pub Date : 2017-12-01 DOI: 10.1109/ICM.2017.8268814

Y. Erhel, N. Amiot, D. Lemur, F. Marie, M. Oger

引用次数: 1

An improved design for high speed analog applications of the fully differential operational floating conveyor 一个改进的设计，高速模拟应用的全差分操作浮动输送机

2017 29th International Conference on Microelectronics (ICM) Pub Date : 2017-12-01 DOI: 10.1109/ICM.2017.8268890

Hossam ElGemmazy, A. Helmy, H. Mostafa, Y. Ismail

引用次数: 0

Conception and realization of highly selective band-pass filters in Ka-band built on thin polymer films 基于聚合物薄膜的ka波段高选择性带通滤波器的构想与实现

2017 29th International Conference on Microelectronics (ICM) Pub Date : 2017-12-01 DOI: 10.1109/ICM.2017.8268896

M. E. Gibari, S. Bretin, Patrick Derval, S. Ginestar, Guillaume Lirzin, Hongwu Li

引用次数: 0

Design of a time-based capacitance-to-digital converter using current starved inverters 基于时间的电容-数字转换器的设计

2017 29th International Conference on Microelectronics (ICM) Pub Date : 2017-12-01 DOI: 10.1109/ICM.2017.8268882

A. Fouad, Y. Ismail, H. Mostafa

{"title":"Design of a time-based capacitance-to-digital converter using current starved inverters","authors":"A. Fouad, Y. Ismail, H. Mostafa","doi":"10.1109/ICM.2017.8268882","DOIUrl":"https://doi.org/10.1109/ICM.2017.8268882","url":null,"abstract":"This paper presents a new design methodology of time-based capacitance-to-digital converters (T-CDCs). The sensor capacitance is the load capacitance of a voltage-to-time converter (VTC) circuit based on current starved inverters. The VTC circuit used has improved sensitivity, linearity and dynamic range. The time delay provided by the VTC circuit is buffered providing a time pulse proportional to the sensor capacitance (Cs). Thus, the VTC circuit becomes a capacitance-to-time converter (CTC) circuit. The time pulse is then digitized using a time-to-digital converter (TDC) circuit providing an output digital code proportional to the sensor capacitance. The output digital code is PVT calibrated using a reference capacitor (Cref). The proposed T-CDC system is a time-based ADC, but with the sensor capacitance as the load capacitance of the used VTC circuit and the input voltages of the current starved inverters in the VTC circuit are fixed and used for biasing. The prototype of the proposed T-CDC is implemented in UMC 130 nm CMOS technology. The T-CDC system is clocked with a 1-MHz clock signal to the VTC circuit. Experimental results show that for a 1 ns counting cycle of the TDC circuit, the system achieves a 8.5-bit resolution and consumes 20 μW with an energy efficiency figure-of-merit (FoM) of 55 fJ/step and a conversion time of 1 μs.","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132270283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A low-noise voltage-controlled ring oscillator in 28-nm FDSOI technology 采用28纳米FDSOI技术的低噪声压控环形振荡器

2017 29th International Conference on Microelectronics (ICM) Pub Date : 2017-12-01 DOI: 10.1109/ICM.2017.8268826

Hussein Bazzi, Mohammad Abou Chanine, Ali Mohsen, A. Harb

引用次数: 3