Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems最新文献

Transient fault sensitivity analysis of analog-to-digital converters (ADCs) 模数转换器(adc)暂态故障灵敏度分析

Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems Pub Date : 2001-04-19 DOI: 10.1109/IWV.2001.923153

Mandeep Singh, R. Rachala, I. Koren

引用次数: 15

A heterogeneous multiprocessor architecture for low-power audio signal processing applications 用于低功耗音频信号处理应用的异构多处理器体系结构

Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems Pub Date : 2001-04-19 DOI: 10.1109/IWV.2001.923139

O. Paker, Jens Sparsø, Niels Haandbæk, Mogens Isager, L. S. Nielsen

{"title":"A heterogeneous multiprocessor architecture for low-power audio signal processing applications","authors":"O. Paker, Jens Sparsø, Niels Haandbæk, Mogens Isager, L. S. Nielsen","doi":"10.1109/IWV.2001.923139","DOIUrl":"https://doi.org/10.1109/IWV.2001.923139","url":null,"abstract":"This paper describes a low-power programmable DSP architecture that targets audio signal processing. The architecture can be characterized as a heterogeneous multiprocessor consisting of small and simple instruction set processors called mini-cores that communicate using message passing. The processors are tailored for different classes of filtering algorithms (FIR, IIR, N-LMS etc.), and in a typical system the communication among processors occurs at the sampling rate only. The processors are parameterized in word-size, memory-size, etc. and can be instantiated according to the needs of the application at hand using a normal synthesis based ASIC design flow. To give an impression of the size of a processor we mention that one of the FIR processors in a prototype design has 16 instructions, a 32 word/spl times/16 bit program memory, a 64 word/spl times/16 bit data memory and a 25 word/spl times/16 bit coefficient memory. Early results obtained from the design of a prototype chip containing filter processors for a hearing aid application, indicate a power consumption that is an order of magnitude better than current state of the art low-power audio DSPs implemented using full-custom techniques. This is due to: (1) the small size of the processors and (2) a smaller instruction count for a given task.","PeriodicalId":114059,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems","volume":"8 Suppl 10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130341961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

A memory management approach for efficient implementation of multimedia kernels on programmable architectures 一种在可编程架构上有效实现多媒体内核的内存管理方法

Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems Pub Date : 2001-04-19 DOI: 10.1109/IWV.2001.923157

M. Dasigenis, N. Kroupis, A. Argyriou, K. Tatas, D. Soudris, A. Thanailakis, N. Zervas

引用次数: 12

Electronic nanotechnology and reconfigurable computing 电子纳米技术和可重构计算

Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems Pub Date : 2001-04-19 DOI: 10.1109/IWV.2001.923133

S. Goldstein

引用次数: 11

A hybrid wave-pipelined network router 混合波管道网络路由器

Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems Pub Date : 2001-04-19 DOI: 10.1109/IWV.2001.923156

J. Delgado-Frías, J. Nyathi

{"title":"A hybrid wave-pipelined network router","authors":"J. Delgado-Frías, J. Nyathi","doi":"10.1109/IWV.2001.923156","DOIUrl":"https://doi.org/10.1109/IWV.2001.923156","url":null,"abstract":"In this paper a novel hybrid wave-pipelined bit-pattern associative router is presented. A router is an important component in communication network systems. The bit-pattern associative router (BPAR) allows for flexibility and can accommodate a large number of routing algorithms. Wave-pipelining is a high performance approach which implements pipelining in logic without using intermediate registers. In this study a hybrid wave-pipelined approach has been proposed and implemented. Hybrid wave-pipelining allows for the reduction of the delay difference between the maximum and minimum delays by narrowing the gap between each stage of the system. This approach yields narrow \"computing cones\" that allow faster clocks to be run. This is the first study in wave-pipelining that deals with a system that has a substantially different set of pipeline stages. The bit-pattern associative router has three stages: condition match, selection function, and port assignment. Each stage's data delay paths are tightly controlled to optimize the proper propagation of signals. The simulation results show that using hybrid wave-pipelining significantly reduces the clock period and circuit delays become the limiting factor, preventing further clock cycle time reduction.","PeriodicalId":114059,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122384327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19

System design of low-energy wearable computers with wireless networking 具有无线网络的低能耗可穿戴计算机系统设计

Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems Pub Date : 2001-04-19 DOI: 10.1109/IWV.2001.923135

A. Smailagic, D. Siewiorek, M. Ettus

引用次数: 7

Evaluating metastability in electronic circuits for random number generation 评估电子电路中用于随机数产生的亚稳态

Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems Pub Date : 2001-04-19 DOI: 10.1109/IWV.2001.923146

S. Walker, S. Foo

引用次数: 18

A linear threshold gate implementation in single electron technology 单电子技术中线性阈值门的实现

Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems Pub Date : 2001-04-19 DOI: 10.1109/IWV.2001.923145

C. Lageweg, S. Cotofana, S. Vassiliadis

引用次数: 116

LUT-based FPGA technology mapping for power minimization with optimal depth 基于lut的FPGA技术映射的最优深度功耗最小化

Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems Pub Date : 2001-04-19 DOI: 10.1109/IWV.2001.923150

Hao Li, Wai-Kei Mak, S. Katkoori

引用次数: 25

Reducing register and phase requirements for synchronous circuits derived using software pipelining techniques 利用软件流水线技术，减少同步电路的寄存器和相位要求

Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems Pub Date : 2001-04-19 DOI: 10.1109/IWV.2001.923142

N. Chabini, E. Aboulhamid, Y. Savaria

{"title":"Reducing register and phase requirements for synchronous circuits derived using software pipelining techniques","authors":"N. Chabini, E. Aboulhamid, Y. Savaria","doi":"10.1109/IWV.2001.923142","DOIUrl":"https://doi.org/10.1109/IWV.2001.923142","url":null,"abstract":"A method based on a modulo scheduling algorithm for software pipelining has been recently proposed to optimize clocked circuits. The resulting circuits are multi-phase clocked circuits, where all clocks have the same period. To preserve the functionality of the original circuit, registers must be placed after minimizing the clock period. The placement of these registers is derived from an arbitrary schedule determined during a clock period minimization step. A good schedule may allow one to decrease the number of registers and the number of phases needed in the final circuit. Decreasing the number of registers contributes to minimizing the area occupied by the circuit and reduces its power consumption; while decreasing the number of phases reduces the complexity of the clock generation and distribution task. In this paper, we propose polynomial-time-solvable methods to choose a good schedule once the clock period is minimized. The methods have been tested on a subject of the ISCAS89 benchmarks. Experimental results show that the number of registers which must be inserted in the final circuit, and the number of phases, have been significantly decreased compared to the case where an arbitrary schedule is chosen.","PeriodicalId":114059,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124358563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7