混合波管道网络路由器

J. Delgado-Frías, J. Nyathi
{"title":"混合波管道网络路由器","authors":"J. Delgado-Frías, J. Nyathi","doi":"10.1109/IWV.2001.923156","DOIUrl":null,"url":null,"abstract":"In this paper a novel hybrid wave-pipelined bit-pattern associative router is presented. A router is an important component in communication network systems. The bit-pattern associative router (BPAR) allows for flexibility and can accommodate a large number of routing algorithms. Wave-pipelining is a high performance approach which implements pipelining in logic without using intermediate registers. In this study a hybrid wave-pipelined approach has been proposed and implemented. Hybrid wave-pipelining allows for the reduction of the delay difference between the maximum and minimum delays by narrowing the gap between each stage of the system. This approach yields narrow \"computing cones\" that allow faster clocks to be run. This is the first study in wave-pipelining that deals with a system that has a substantially different set of pipeline stages. The bit-pattern associative router has three stages: condition match, selection function, and port assignment. Each stage's data delay paths are tightly controlled to optimize the proper propagation of signals. The simulation results show that using hybrid wave-pipelining significantly reduces the clock period and circuit delays become the limiting factor, preventing further clock cycle time reduction.","PeriodicalId":114059,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"19","resultStr":"{\"title\":\"A hybrid wave-pipelined network router\",\"authors\":\"J. Delgado-Frías, J. Nyathi\",\"doi\":\"10.1109/IWV.2001.923156\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper a novel hybrid wave-pipelined bit-pattern associative router is presented. A router is an important component in communication network systems. The bit-pattern associative router (BPAR) allows for flexibility and can accommodate a large number of routing algorithms. Wave-pipelining is a high performance approach which implements pipelining in logic without using intermediate registers. In this study a hybrid wave-pipelined approach has been proposed and implemented. Hybrid wave-pipelining allows for the reduction of the delay difference between the maximum and minimum delays by narrowing the gap between each stage of the system. This approach yields narrow \\\"computing cones\\\" that allow faster clocks to be run. This is the first study in wave-pipelining that deals with a system that has a substantially different set of pipeline stages. The bit-pattern associative router has three stages: condition match, selection function, and port assignment. Each stage's data delay paths are tightly controlled to optimize the proper propagation of signals. The simulation results show that using hybrid wave-pipelining significantly reduces the clock period and circuit delays become the limiting factor, preventing further clock cycle time reduction.\",\"PeriodicalId\":114059,\"journal\":{\"name\":\"Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems\",\"volume\":\"24 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-04-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"19\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IWV.2001.923156\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWV.2001.923156","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 19

摘要

本文提出了一种新型的混合波管道式位模式关联路由器。路由器是通信网络系统的重要组成部分。位模式关联路由器(BPAR)具有灵活性,可以容纳大量的路由算法。波形流水线是一种高性能的方法,它在逻辑上实现流水线,而不使用中间寄存器。本文提出并实现了一种混合波管道方法。混合波管道允许通过缩小系统每个阶段之间的差距来减少最大和最小延迟之间的延迟差异。这种方法产生狭窄的“计算锥”,允许更快的时钟运行。这是第一次对波浪管道系统进行研究,该系统具有完全不同的管道级集。位模式关联路由器有三个阶段:条件匹配、选择功能和端口分配。每个阶段的数据延迟路径被严格控制,以优化信号的适当传播。仿真结果表明,采用混合波管道可以显著缩短时钟周期,电路延迟成为限制因素,阻止了时钟周期时间的进一步缩短。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A hybrid wave-pipelined network router
In this paper a novel hybrid wave-pipelined bit-pattern associative router is presented. A router is an important component in communication network systems. The bit-pattern associative router (BPAR) allows for flexibility and can accommodate a large number of routing algorithms. Wave-pipelining is a high performance approach which implements pipelining in logic without using intermediate registers. In this study a hybrid wave-pipelined approach has been proposed and implemented. Hybrid wave-pipelining allows for the reduction of the delay difference between the maximum and minimum delays by narrowing the gap between each stage of the system. This approach yields narrow "computing cones" that allow faster clocks to be run. This is the first study in wave-pipelining that deals with a system that has a substantially different set of pipeline stages. The bit-pattern associative router has three stages: condition match, selection function, and port assignment. Each stage's data delay paths are tightly controlled to optimize the proper propagation of signals. The simulation results show that using hybrid wave-pipelining significantly reduces the clock period and circuit delays become the limiting factor, preventing further clock cycle time reduction.
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