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Radio receiver mixer model for event-driven simulators to support functional verification of RF-SOC wireless links 事件驱动模拟器的无线电接收机混频器模型，以支持RF-SOC无线链路的功能验证
2010 IEEE International Behavioral Modeling and Simulation Workshop Pub Date : 2010-09-01 DOI: 10.1109/BMAS.2010.6156596
J. David
{"title":"Radio receiver mixer model for event-driven simulators to support functional verification of RF-SOC wireless links","authors":"J. David","doi":"10.1109/BMAS.2010.6156596","DOIUrl":"https://doi.org/10.1109/BMAS.2010.6156596","url":null,"abstract":"The baseband-equivalent approach is used to derive a SystemVerilog model of a double-balanced receiver mixer to support functional verification of the transceiver block in a wireless communications integrated circuit. Results using the transceiver model at the chip verification level are reported.","PeriodicalId":112947,"journal":{"name":"2010 IEEE International Behavioral Modeling and Simulation Workshop","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131768619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
System verification of flexray communication networks through behavioral simulations flexray通信网络的行为模拟系统验证
2010 IEEE International Behavioral Modeling and Simulation Workshop Pub Date : 2010-09-01 DOI: 10.1109/BMAS.2010.6156589
Candice Müller, M. Valle
{"title":"System verification of flexray communication networks through behavioral simulations","authors":"Candice Müller, M. Valle","doi":"10.1109/BMAS.2010.6156589","DOIUrl":"https://doi.org/10.1109/BMAS.2010.6156589","url":null,"abstract":"Internal vehicle communication networks are becoming highly distributed systems. The increase of the internal vehicle electronic system complexity requires higher performance and reliability, and the necessity of ensuring enough bus signal integrity increases the design verification effort. In this paper we present a system verification methodology of Flexray communication networks through behavioral simulations as well as the analysis of important parameters which influence the communication. The paper presents the verification of different network topologies through mixed-mode behavioral simulations and the evaluation of the most critical aspects of the physical layer. Modifications in the original topologies have been performed, and their effects have been analyzed. Additionally, we give special attention to the computational effort required for the behavioral simulations. The different topologies have been simulated with two bus line models (a lossless and a lossy), and the results are evaluated in terms of CPU usage time and accuracy.","PeriodicalId":112947,"journal":{"name":"2010 IEEE International Behavioral Modeling and Simulation Workshop","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122101594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Fault injection in mixed-signal environment using behavioral fault modeling in Verilog-A 基于Verilog-A的行为故障建模在混合信号环境中的故障注入
2010 IEEE International Behavioral Modeling and Simulation Workshop Pub Date : 2010-09-01 DOI: 10.1109/BMAS.2010.6156601
S. N. Ahmadian, S. Miremadi
{"title":"Fault injection in mixed-signal environment using behavioral fault modeling in Verilog-A","authors":"S. N. Ahmadian, S. Miremadi","doi":"10.1109/BMAS.2010.6156601","DOIUrl":"https://doi.org/10.1109/BMAS.2010.6156601","url":null,"abstract":"Fault injection methods have been used for analyzing dependability characteristics of systems for years. In this paper we propose a practical mixed-signal fault injection flow that is fast as well as accurate. We described three classes of most common faults: i) Single event transients, ii) Electro-Magnetic interference and iii) Power disturbance faults. Fault models are implemented directly into circuit's devices using behavioral fault description in Verilog-A language. As an example for dependability evaluation, some test circuits have been prepared and the results of fault injection on their designs have been reported.","PeriodicalId":112947,"journal":{"name":"2010 IEEE International Behavioral Modeling and Simulation Workshop","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124054765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Automatic stress effects computation based on a layout generation tool for analog IC 基于布局生成工具的模拟集成电路应力效应自动计算
2010 IEEE International Behavioral Modeling and Simulation Workshop Pub Date : 2010-09-01 DOI: 10.1109/BMAS.2010.6156590
Stephanie Youssef, D. Dupuis, R. Iskander, M. Louërat
{"title":"Automatic stress effects computation based on a layout generation tool for analog IC","authors":"Stephanie Youssef, D. Dupuis, R. Iskander, M. Louërat","doi":"10.1109/BMAS.2010.6156590","DOIUrl":"https://doi.org/10.1109/BMAS.2010.6156590","url":null,"abstract":"This paper studies the matching and the stress effect problems that appear in deep submicron CMOS technologies. These effects significantly affect the electrical behavior of CMOS transistors. We propose a method to compute stress effect parameters resulting from different layout styles such as interdigitated and symmetrical styles. We apply this method to a transistor device and a differential pair device. We also quantify the errors due to transistor folding and stress effects in 65nm CMOS technology for different device layouts. The results show the effectiveness of the proposed method.","PeriodicalId":112947,"journal":{"name":"2010 IEEE International Behavioral Modeling and Simulation Workshop","volume":"170 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127556937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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