发布求助
文献互助 智能选刊 最新文献

2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)最新文献

筛选
英文 中文
A 16-bit Audio Continuous-Time Sigma-Delta Modulator Using VCO-based Quantizer 基于vco量化器的16位音频连续时间σ - δ调制器
2018 16th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2018-06-01 DOI: 10.1109/NEWCAS.2018.8585642
Anthony Baltolu, D. Dallet, F. Chalet, Xavier Albinet, J. Bégueret
{"title":"A 16-bit Audio Continuous-Time Sigma-Delta Modulator Using VCO-based Quantizer","authors":"Anthony Baltolu, D. Dallet, F. Chalet, Xavier Albinet, J. Bégueret","doi":"10.1109/NEWCAS.2018.8585642","DOIUrl":"https://doi.org/10.1109/NEWCAS.2018.8585642","url":null,"abstract":"This paper presents a third-order continuous-time sigma-delta modulator for an audio application (16-bit dynamic range is targeted). It uses a multibit VCO-based quantizer to benefit from its properties: adding one noise-shaping order and mostly digital implementation saving power and area. Even if VCO linearity typically limits its application to medium resolution converters, using it as the last stage of a continuous-time modulator allows to extend its application range even in high-resolution designs. For low-power issue, a second-order single-opamp loop filter is adopted as well as a tri-level DAC switching scheme with specific DWA. The design implemented in a $140nm$ standard CMOS technology reaches $98dB$ dynamic range in a $20kHz$ bandwidth for a $142mu W$ power consumption. This results in a Schreier FOM11FOM = DRdB + 10 × log (Bandwidth/Power) of $179. 5dB$ which places the proposed modulator among the state-of-the-art designs.","PeriodicalId":112526,"journal":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131461953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Ultra High-Speed Hardware Emulator for Real-Time Fault Location in Multi-Conductor Power Systems 多导体电力系统实时故障定位的超高速硬件仿真
2018 16th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2018-06-01 DOI: 10.1109/NEWCAS.2018.8585599
François Gaugaz, F. Krummenacher, M. Kayal
{"title":"Ultra High-Speed Hardware Emulator for Real-Time Fault Location in Multi-Conductor Power Systems","authors":"François Gaugaz, F. Krummenacher, M. Kayal","doi":"10.1109/NEWCAS.2018.8585599","DOIUrl":"https://doi.org/10.1109/NEWCAS.2018.8585599","url":null,"abstract":"This research presents a transmission line model aimed for the fault location in power systems using a method based on the Electromagnetic Time-Reversal (EMTR). The discrete-time model simulates the waves travelling in the line by means of many unit delays implemented with digital $N_{b}$ bits shift registers. The flexibility and robustness of this fully digital realization are discussed and compared to previous analog implementations and evaluated in the frame of the fault location. The impact of the signal quantization on the fault location accuracy is therefore discussed. An extension of the line model for the simulation of more complex network topologies, such as interconnected or multi-conductor networks is also presented. It is then shown that a fault on a three-conductor line can be located within few tens of milliseconds with a resolution of 1%, considering the model implemented in a TSMC 0.18$mu$m process. Through this is speed improvement, about a hundred times faster than classical digital solvers, this promising approach makes real-time implementation realistic.","PeriodicalId":112526,"journal":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130489259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Non-Linear Sequential SVM Classifier of Epileptic Seizures 癫痫发作的非线性序列SVM分类器
2018 16th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2018-06-01 DOI: 10.1109/NEWCAS.2018.8585693
Mohamed G. Egila, E. B. Assi, M. Sawan
{"title":"Non-Linear Sequential SVM Classifier of Epileptic Seizures","authors":"Mohamed G. Egila, E. B. Assi, M. Sawan","doi":"10.1109/NEWCAS.2018.8585693","DOIUrl":"https://doi.org/10.1109/NEWCAS.2018.8585693","url":null,"abstract":"This paper concerns a design for implementing Support Vector Machine (SVM), with non-linear Gaussian kernel on Field Programmable Gate Array (FPGA), for development of an accurate seizure epilepsy classification. The proposed methodology depends on storing the extracted support vectors, along with the SVM parameters into Lookup Tables. The proposed SVM architecture depends on feeding the selected support vectors into a single Gaussian kernel core in a sequential fashion, rather than feeding them parallely to the kernel cores, thus reducing the resources usage on the target FPGA board. The system is implemented on Xilinx Virtex6 xc6vcx75t board. System verifications and simulations have been done. The proposed methodology achieves accuracy of 88.53%, along with average sensitivity and specificity of 86.4% and 90.83% respectively.","PeriodicalId":112526,"journal":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"18 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114103260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Low Power CORDIC-Based Hardware Implementation of Izhikevich Neuron Model 基于cordic的Izhikevich神经元模型的低功耗硬件实现
2018 16th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2018-06-01 DOI: 10.1109/NEWCAS.2018.8585485
Abdelrahim Elnabawy, H. Abdelmohsen, M. Moustafa, Mostafa Elbediwy, A. Helmy, H. Mostafa
{"title":"A Low Power CORDIC-Based Hardware Implementation of Izhikevich Neuron Model","authors":"Abdelrahim Elnabawy, H. Abdelmohsen, M. Moustafa, Mostafa Elbediwy, A. Helmy, H. Mostafa","doi":"10.1109/NEWCAS.2018.8585485","DOIUrl":"https://doi.org/10.1109/NEWCAS.2018.8585485","url":null,"abstract":"In this paper, an efficient CORDIC-based hardware implementation of the Izhikevich neuron model is introduced. The CORDIC (COordinate Rotation Digital Computer) algorithm is used to approximate the square term in Izhikevich equations that describe the neuron response. The approximation is evaluated by defining four types of errors where the CORDIC approximation shows significant improvement in error performance compared to the Piecewise Linear (PWL) model [1]. The power consumption of the CORDIC-based neuron hardware implementation ranges from 0.26 mW to 0.4 mW whereas the PWL-based neuron as well as the original Izhikevich neuron hardware implementations consume 0.3 mW and 1.06 mW, respectively. A Figure of Merit (FoM) is defined to show the tradeoff among errors, power and area. By comparing with the PWL-based neuron hardware implementation, it is found that the CORDIC-based model is preferred as an approximation method from the error, power and area perspective.","PeriodicalId":112526,"journal":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121373280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Skew Reduction on a long transmission line using multiple local DLLs for high-speed imagery 使用多个本地dll减少高速图像的长传输线上的倾斜
2018 16th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2018-06-01 DOI: 10.1109/NEWCAS.2018.8585683
J. Kammerer, Octavian Maciu, Imane Malass, J. L. Normand, W. Uhring
{"title":"Skew Reduction on a long transmission line using multiple local DLLs for high-speed imagery","authors":"J. Kammerer, Octavian Maciu, Imane Malass, J. L. Normand, W. Uhring","doi":"10.1109/NEWCAS.2018.8585683","DOIUrl":"https://doi.org/10.1109/NEWCAS.2018.8585683","url":null,"abstract":"A transmission line induced skew reduction system for shutter signals of a pixel array has been designed using TowerJazz CIS 0.18m technology. It is based on the use of multiple delay-locked loop in charge of close-to-close synchronization. The simulation results demonstrate the ability of the system to compensate the transmission line induced skew from 1.58ns to 75ps. The measurements made with a prototype integrating a 11.6mm servo-controlled transmission line and fours delay-locked loop demonstrated a reduction of its skew down to 32ps.","PeriodicalId":112526,"journal":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116267100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 60-GHz CMOS Down-Conversion Mixer with High Conversion Gain and Low Noise Figure 具有高转换增益和低噪声系数的60 ghz CMOS下变频混频器
2018 16th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2018-06-01 DOI: 10.1109/NEWCAS.2018.8585584
M. Kashani, A. Tarkeshdouz, E. Afshari, S. Mirabbasi
{"title":"A 60-GHz CMOS Down-Conversion Mixer with High Conversion Gain and Low Noise Figure","authors":"M. Kashani, A. Tarkeshdouz, E. Afshari, S. Mirabbasi","doi":"10.1109/NEWCAS.2018.8585584","DOIUrl":"https://doi.org/10.1109/NEWCAS.2018.8585584","url":null,"abstract":"In this paper, we present a 60-GHz single-balanced CMOS down-conversion mixer. The proposed mixer uses an on-chip active balun to furnish a differential output from an injected single-ended local oscillator (LO) signal. The millimeter-wave (mm-wave) active balun incorporates a cascode cross-coupled structure to generate the differential LO with a high voltage gain and minimum amplitude and phase mismatch. The overall mixer achieves a high conversion gain (CG) with a linearity and noise-figure performance that compare favorably with those of state-of-the-art designs. As a proof-of-concept, a 60-GHz mixer with a center intermediate-frequency (IF) of 20 GHz and output bandwidth of 3.2 GHz is designed and implemented in a 65-nm CMOS process. Measurement results show that the mixer achieves a peak conversion gain of $12.1~dB$ and 1-dB compression point of $-5dBm$. Furthermore, the fabricated mixer achieves a minimum double-sideband (DSB) noise figure of $6.5~dB$ over the bandwidth of interest. The chip consumes $11.5~mW$ from a 1-V supply and excluding the pads occupies $0.27~mm^{2}$ of silicon area.","PeriodicalId":112526,"journal":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123284364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
NEWCAS 2018 Commentary
2018 16th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2018-06-01 DOI: 10.1109/newcas.2018.8585608
{"title":"NEWCAS 2018 Commentary","authors":"","doi":"10.1109/newcas.2018.8585608","DOIUrl":"https://doi.org/10.1109/newcas.2018.8585608","url":null,"abstract":"","PeriodicalId":112526,"journal":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122691218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
NEWCAS 2018 Index
2018 16th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2018-06-01 DOI: 10.1109/newcas.2018.8585707
{"title":"NEWCAS 2018 Index","authors":"","doi":"10.1109/newcas.2018.8585707","DOIUrl":"https://doi.org/10.1109/newcas.2018.8585707","url":null,"abstract":"","PeriodicalId":112526,"journal":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127457298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Modeling Surface Recombination with Enhanced Devices Network for Optoelectronics 基于增强器件网络的光电子学表面复合建模
2018 16th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2018-06-01 DOI: 10.1109/NEWCAS.2018.8585606
Chiara Rossi, P. Buccella, C. Stefanucci, J. Sallese
{"title":"Modeling Surface Recombination with Enhanced Devices Network for Optoelectronics","authors":"Chiara Rossi, P. Buccella, C. Stefanucci, J. Sallese","doi":"10.1109/NEWCAS.2018.8585606","DOIUrl":"https://doi.org/10.1109/NEWCAS.2018.8585606","url":null,"abstract":"We present a lumped devices network approach to simulate surface recombination effects in optoelectronics devices. The network is composed of generalized lumped devices where the excess carrier concentrations and gradients are mapped on electrical quantities, i.e. equivalent voltages and currents respectively, so that the overall simulation is SPICE-compatible. A novel enhanced device is derived and used as an additional element to account for the influence of the surface in SPICE-like simulations. Thus, in addition to generation, propagation and collection that were included in a former work, recombination at the surface of the semiconductor can be taken into account with standard circuit simulators. Optoelectronic devices performance degradation due to surface recombination is analyzed with this approach and compared with full numerical TCAD simulations.","PeriodicalId":112526,"journal":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130673637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Using the Characteristic Value of the Body Channel for Encryption of Body Area Networks 利用主体信道的特征值对主体区域网络进行加密
2018 16th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2018-06-01 DOI: 10.1109/NEWCAS.2018.8585553
Junchao Wang, Kaining Han, Anastasios Alexandridis, Z. Zilic, Tong Bai, Jinzhao Lin, Yu Pang, Guoquan Li
{"title":"Using the Characteristic Value of the Body Channel for Encryption of Body Area Networks","authors":"Junchao Wang, Kaining Han, Anastasios Alexandridis, Z. Zilic, Tong Bai, Jinzhao Lin, Yu Pang, Guoquan Li","doi":"10.1109/NEWCAS.2018.8585553","DOIUrl":"https://doi.org/10.1109/NEWCAS.2018.8585553","url":null,"abstract":"Body area network (BAN) consists of intercommunicating sensors, which are either wearable, or can be implanted into the human body. Being a network that features critical information, BAN requires encryption, however common encryption methods found in computer networks are not ideal due to complex algorithms and high power consumption. The authors propose a new encryption method based on the human body channel. This new encryption method has the advantages of low-power, dynamic updating, rapid operation, and easy implementation, which is suitable for BAN systems.","PeriodicalId":112526,"journal":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127069382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信