Power-Aware Computer Systems最新文献

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Simultaneous multithreading on x86_64 systems: an energy efficiency evaluation x86_64系统上的同步多线程:能效评估
Power-Aware Computer Systems Pub Date : 2011-10-23 DOI: 10.1145/2039252.2039262
R. Schöne, D. Hackenberg, Daniel Molka
{"title":"Simultaneous multithreading on x86_64 systems: an energy efficiency evaluation","authors":"R. Schöne, D. Hackenberg, Daniel Molka","doi":"10.1145/2039252.2039262","DOIUrl":"https://doi.org/10.1145/2039252.2039262","url":null,"abstract":"In recent years, power consumption has become one of the most important design criteria for microprocessors. CPUs are therefore no longer developed with a narrow focus on raw compute performance. This means that well-established processor features that have proven to increase compute performance now need to be re-evaluated with a new focus on energy efficiency. This paper presents an energy efficiency evaluation of the symmetric multithreading (SMT) feature on state-of-the-art x86_64 processors. We use a mature power measurement methodology to analyze highly sophisticated low-level microbenchmarks as well as a diverse set of application benchmarks. Our results show that--depending on the workload--SMT can be at the same time advantageous in terms of performance and disadvantageous in terms of energy efficiency. Moreover, we demonstrate how the SMT efficiency has advanced between two processor generations.","PeriodicalId":112226,"journal":{"name":"Power-Aware Computer Systems","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115258476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Towards realizing a low cost and highly available datacenter power infrastructure 朝着实现低成本、高可用性的数据中心电力基础设施迈进
Power-Aware Computer Systems Pub Date : 2011-10-23 DOI: 10.1145/2039252.2039259
Sriram Govindan, Di Wang, L. Chen, A. Sivasubramaniam, B. Urgaonkar
{"title":"Towards realizing a low cost and highly available datacenter power infrastructure","authors":"Sriram Govindan, Di Wang, L. Chen, A. Sivasubramaniam, B. Urgaonkar","doi":"10.1145/2039252.2039259","DOIUrl":"https://doi.org/10.1145/2039252.2039259","url":null,"abstract":"Realizing highly available datacenter power infrastructure is an extremely expensive proposition with costs more than doubling as we move from three 9's (Tier-1) to six 9's (Tier-4) of availability. Existing approaches only consider the cost/availability trade-off for a restricted set of power infrastructure configurations, relying mainly on component redundancy. A number of additional knobs such as centralized vs. distributed component placement and power-feed interconnect topology also exist, whose impact has only been studied in limited forms. In this paper, we develop detailed datacenter availability models using Continuous-time Markov Chains and Reliability Block Diagrams to quantify the cost-availability trade-off offered by these power infrastructure knobs.","PeriodicalId":112226,"journal":{"name":"Power-Aware Computer Systems","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129951732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
Leveraging thermal storage to cut the electricity bill for datacenter cooling 利用热存储来减少数据中心冷却的电费
Power-Aware Computer Systems Pub Date : 2011-10-23 DOI: 10.1145/2039252.2039260
Yefu Wang, Xiaorui Wang, Yanwei Zhang
{"title":"Leveraging thermal storage to cut the electricity bill for datacenter cooling","authors":"Yefu Wang, Xiaorui Wang, Yanwei Zhang","doi":"10.1145/2039252.2039260","DOIUrl":"https://doi.org/10.1145/2039252.2039260","url":null,"abstract":"The electricity cost of cooling systems can account for 30% of the total electricity bill of operating a data center. While many prior studies have tried to reduce the cooling energy in data centers, they cannot effectively utilize the time-varying power prices in the power market to cut the electricity bill of data center cooling. Thermal storage techniques have provided opportunities to store cooling energy in ice or water-based tanks or overcool the data center when the power price is relatively low. Consequently, when the power price is high, data centers can choose to use less electricity from power grid for cooling, resulting in a significantly reduced electricity bill.\u0000 In this paper, we design and evaluate TStore, a cooling strategy that leverages thermal storage to cut the electricity bill for cooling, without causing servers in a data center to overheat. TStore checks the low prices in the hourahead power market and overcools the thermal masses in the datacenter, which can then absorb heat when the power price increases later. On a longer time scale, TStore is integrated with auxiliary thermal storage tanks, which are recently adopted by some data-centers to store energy in the form of ice when the power price is low at night, such that the stored ice can be used to cool the datacenter in daytime. We model the impacts of TStore on server temperatures based on Computational Fluid Dynamics (CFD) to consider the realistic thermal dynamics in a data center with 1,120 servers. We then evaluate TStore using workload traces from real-world data centers and power price traces from a real power market. Our results show that TStore achieves the desired cooling performance with a 16.8% less electricity bill than the current practice.","PeriodicalId":112226,"journal":{"name":"Power-Aware Computer Systems","volume":"48 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132090844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
The case for sleep states in servers 服务器的睡眠状态
Power-Aware Computer Systems Pub Date : 2011-10-23 DOI: 10.1145/2039252.2039254
Anshul Gandhi, Mor Harchol-Balter, M. Kozuch
{"title":"The case for sleep states in servers","authors":"Anshul Gandhi, Mor Harchol-Balter, M. Kozuch","doi":"10.1145/2039252.2039254","DOIUrl":"https://doi.org/10.1145/2039252.2039254","url":null,"abstract":"While sleep states have existed for mobile devices and workstations for some time, these sleep states have largely not been incorporated into the servers in today's data centers.\u0000 Chip designers have been unmotivated to design sleep states because data center administrators haven't expressed any desire to have them. High setup times make administrators fearful of any form of dynamic power management, whereby servers are suspended or shut down when load drops. This general reluctance has stalled research into whether there might be some feasible sleep state (with sufficiently low setup overhead and/or sufficiently low power) that would actually be beneficial in data centers.\u0000 This paper uses both experimentation and theory to investigate the regime of sleep states that should be advantageous in data centers. Implementation experiments involve a 24-server multi-tier testbed, serving a web site of the type seen in Facebook or Amazon with key-value workload and a range of hypothetical sleep states. Analytical modeling is used to understand the effect of scaling up to larger data centers. The goal of this research is to encourage data center administrators to consider dynamic power management and to spur chip designers to develop useful sleep states for servers.","PeriodicalId":112226,"journal":{"name":"Power-Aware Computer Systems","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116444545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
Ekho: bridging the gap between simulation and reality in tiny energy-harvesting sensors Ekho:在微型能量收集传感器中弥合模拟与现实之间的差距
Power-Aware Computer Systems Pub Date : 2011-10-23 DOI: 10.1145/2039252.2039261
Hong Zhang, M. Salajegheh, Kevin Fu, Jacob M. Sorber
{"title":"Ekho: bridging the gap between simulation and reality in tiny energy-harvesting sensors","authors":"Hong Zhang, M. Salajegheh, Kevin Fu, Jacob M. Sorber","doi":"10.1145/2039252.2039261","DOIUrl":"https://doi.org/10.1145/2039252.2039261","url":null,"abstract":"Harvested energy makes long-term maintenance-free sensor deployments possible; however, as devices shrink in order to accommodate new applications, tightening energy budgets and increasing power supply volatility leaves system designers poorly equipped to predict how their devices will behave when deployed.\u0000 This paper describes the design and initial FPGA-based implementation of Ekho, a tool that records and emulates energy harvesting conditions, in order to support realistic and repeatable testing and experimentation. Ekho uses the abstraction of I-V curves---curves that describe harvesting current with respect to supply voltage---to accurately represent harvesting conditions, and supports a range of harvesting technologies. An early prototype emulates I-V curves with 0.1mA accuracy, and responds in 4.4μs to changes in energy conditions.","PeriodicalId":112226,"journal":{"name":"Power-Aware Computer Systems","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114914344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
The interplay of software bloat, hardware energy proportionality and system bottlenecks 软件膨胀、硬件能量比例和系统瓶颈的相互作用
Power-Aware Computer Systems Pub Date : 2011-10-23 DOI: 10.1145/2039252.2039253
Suparna Bhattacharya, K. Rajamani, K. Gopinath, Manish Gupta
{"title":"The interplay of software bloat, hardware energy proportionality and system bottlenecks","authors":"Suparna Bhattacharya, K. Rajamani, K. Gopinath, Manish Gupta","doi":"10.1145/2039252.2039253","DOIUrl":"https://doi.org/10.1145/2039252.2039253","url":null,"abstract":"In large flexible software systems, bloat occurs in many forms, causing excess resource utilization and resource bottlenecks. This results in lost throughput and wasted joules. However, mitigating bloat is not easy; efforts are best applied where savings would be substantial. To aid this we develop an analytical model establishing the relation between bottleneck in resources, bloat, performance and power.\u0000 Analyses with the model places into perspective results from the first experimental study of the power-performance implications of bloat. In the experiments we find that while bloat reduction can provide as much as 40% energy savings, the degree of impact depends on hardware and software characteristics. We confirm predictions from our model with selected results from our experimental study.\u0000 Our findings show that a software-only view is inadequate when assessing the effects of bloat. The impact of bloat on physical resource usage and power should be understood for a full systems perspective to properly deploy bloat reduction solutions and reap their power-performance benefits.","PeriodicalId":112226,"journal":{"name":"Power-Aware Computer Systems","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126382028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Bit-Sliced Datapath for Energy-Efficient High Performance Microprocessors 高效节能高性能微处理器的位片数据路径
Power-Aware Computer Systems Pub Date : 2004-12-05 DOI: 10.1007/11574859_3
Sumeet Kumar, Prateek Pujara, Aneesh Aggarwal
{"title":"Bit-Sliced Datapath for Energy-Efficient High Performance Microprocessors","authors":"Sumeet Kumar, Prateek Pujara, Aneesh Aggarwal","doi":"10.1007/11574859_3","DOIUrl":"https://doi.org/10.1007/11574859_3","url":null,"abstract":"","PeriodicalId":112226,"journal":{"name":"Power-Aware Computer Systems","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127737250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization 通过指令封装和标签记忆降低唤醒逻辑的延迟和功耗
Power-Aware Computer Systems Pub Date : 2004-12-05 DOI: 10.1007/11574859_2
J. Sharkey, D. Ponomarev, K. Ghose, O. Ergin
{"title":"Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization","authors":"J. Sharkey, D. Ponomarev, K. Ghose, O. Ergin","doi":"10.1007/11574859_2","DOIUrl":"https://doi.org/10.1007/11574859_2","url":null,"abstract":"","PeriodicalId":112226,"journal":{"name":"Power-Aware Computer Systems","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122254923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
Power Consumption Breakdown on a Modern Laptop 现代笔记本电脑的功耗分析
Power-Aware Computer Systems Pub Date : 2004-12-05 DOI: 10.1007/11574859_12
Aqeel Mahesri, V. Vardhan
{"title":"Power Consumption Breakdown on a Modern Laptop","authors":"Aqeel Mahesri, V. Vardhan","doi":"10.1007/11574859_12","DOIUrl":"https://doi.org/10.1007/11574859_12","url":null,"abstract":"","PeriodicalId":112226,"journal":{"name":"Power-Aware Computer Systems","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133033745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 183
Bus Power Estimation and Power-Efficient Bus Arbitration for System-on-a-Chip Embedded Systems 片上系统嵌入式系统的总线功率估计和高效总线仲裁
Power-Aware Computer Systems Pub Date : 2004-12-05 DOI: 10.1007/11574859_7
K. Ning, D. Kaeli
{"title":"Bus Power Estimation and Power-Efficient Bus Arbitration for System-on-a-Chip Embedded Systems","authors":"K. Ning, D. Kaeli","doi":"10.1007/11574859_7","DOIUrl":"https://doi.org/10.1007/11574859_7","url":null,"abstract":"","PeriodicalId":112226,"journal":{"name":"Power-Aware Computer Systems","volume":"188 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132415599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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