2019 IEEE/ACM 7th International Conference on Formal Methods in Software Engineering (FormaliSE)最新文献_第2页

A Proof-Producing Translator for Verilog Development in HOL 在HOL中开发Verilog的证明生成翻译器

2019 IEEE/ACM 7th International Conference on Formal Methods in Software Engineering (FormaliSE) Pub Date : 2019-05-27 DOI: 10.1109/FormaliSE.2019.00020

Andreas Lööw, Magnus O. Myreen

{"title":"A Proof-Producing Translator for Verilog Development in HOL","authors":"Andreas Lööw, Magnus O. Myreen","doi":"10.1109/FormaliSE.2019.00020","DOIUrl":"https://doi.org/10.1109/FormaliSE.2019.00020","url":null,"abstract":"We present an automatic proof-producing translator targeting the hardware description language Verilog. The tool takes a circuit represented as a HOL function as input, translates the input function to a Verilog program and automatically proves a correspondence theorem between the input function and the output Verilog program ensuring that the translation is correct. As illustrated in the paper, the generated correspondence theorems furthermore enable transporting circuit reasoning from the HOL level to the Verilog level. We also present a formal semantics for the subset of Verilog targeted by the translator, which we have developed in parallel with the translator. The semantics is based on the official Verilog standard and is, unlike previous formalization efforts, designed to be usable for automated and interactive reasoning without sacrificing a clear correspondence to the standard. To illustrate the translator's applicability, we describe case studies of a simple verified processor and verified regexp matchers and synthesize them for two FPGA boards. The development has been carried out in the HOL4 theorem prover.","PeriodicalId":111168,"journal":{"name":"2019 IEEE/ACM 7th International Conference on Formal Methods in Software Engineering (FormaliSE)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125926800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

[Title page i] [标题页i]

2019 IEEE/ACM 7th International Conference on Formal Methods in Software Engineering (FormaliSE) Pub Date : 2019-05-01 DOI: 10.1109/formalise.2019.00001

引用次数: 0

Copyright 版权

2019 IEEE/ACM 7th International Conference on Formal Methods in Software Engineering (FormaliSE) Pub Date : 2019-05-01 DOI: 10.1109/formalise.2019.00003

引用次数: 0

A Generalized Program Verification Workflow Based on Loop Elimination and SA Form 基于循环消去和SA形式的通用程序验证工作流

2019 IEEE/ACM 7th International Conference on Formal Methods in Software Engineering (FormaliSE) Pub Date : 2019-05-01 DOI: 10.1109/FormaliSE.2019.00017

C. Lourenço, M. J. Frade, J. Pinto

{"title":"A Generalized Program Verification Workflow Based on Loop Elimination and SA Form","authors":"C. Lourenço, M. J. Frade, J. Pinto","doi":"10.1109/FormaliSE.2019.00017","DOIUrl":"https://doi.org/10.1109/FormaliSE.2019.00017","url":null,"abstract":"This paper presents a minimal model of the functioning of program verification and property checking tools based on (i) the encoding of loops as non-iterating programs, either conservatively, making use of invariants and assume/assert commands, or in a bounded way; and (ii) the use of an intermediate single-assignment (SA) form. The model captures the basic workflow of tools like Boogie, Why3, or CBMC, building on a clear distinction between operational and axiomatic semantics. This allows us to consider separately the soundness of program annotation, loop encoding, translation into SA form, and VC generation, as well as appropriate notions of completeness for each of these processes. To the best of our knowledge, this is the first formalization of a bounded model checking of software technique, including soundness and completeness proofs using Hoare logic; we also give the first completeness proof of a deductive verification technique based on a conservative encoding of invariant-annotated loops with assume/assert in SA form, as well as the first soundness proof based on a program logic.","PeriodicalId":111168,"journal":{"name":"2019 IEEE/ACM 7th International Conference on Formal Methods in Software Engineering (FormaliSE)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123742532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Message from the Chairs of FormaliSE 2019 来自2019年正式化会议主席的信息

2019 IEEE/ACM 7th International Conference on Formal Methods in Software Engineering (FormaliSE) Pub Date : 2019-05-01 DOI: 10.1109/formalise.2019.00006

引用次数: 0

On the Formalization of Importance Measures Using HOL Theorem Proving 用HOL定理证明重要测度的形式化

2019 IEEE/ACM 7th International Conference on Formal Methods in Software Engineering (FormaliSE) Pub Date : 2019-04-02 DOI: 10.1109/FormaliSE.2019.00021

W. Ahmed, Shahid Ali Murtza, O. Hasan, S. Tahar

{"title":"On the Formalization of Importance Measures Using HOL Theorem Proving","authors":"W. Ahmed, Shahid Ali Murtza, O. Hasan, S. Tahar","doi":"10.1109/FormaliSE.2019.00021","DOIUrl":"https://doi.org/10.1109/FormaliSE.2019.00021","url":null,"abstract":"Importance measures provide a systematic approach to scrutinize critical system components, which are extremely beneficial in making important decisions, such as prioritizing reliability improvement activities, identifying weak-links and effective usage of given resources. The importance measures are then in turn used to obtain a criticality value for each system component and to rank the components in descending manner. Simulations tools are generally used to perform importance measure based analysis, but they require expensive computations and thus they are not suitable for large systems. A more scalable approach is to utilize the importance measures to obtain all the necessary conditions by proving a generic relationship describing the relative importance between any pair of components in a system. In this paper, we propose to use higher-order-logic (HOL) theorem proving to verify such relationships and thus making sure that all the essential conditions are accompanied by the proven property. In particular, we formalize the commonly used importance measures, such as Birnbaum and Fussell-Vesely, and conduct a formal importance measure analysis of a railway signaling system at a Moroccan level crossing as an application for illustration purpose.","PeriodicalId":111168,"journal":{"name":"2019 IEEE/ACM 7th International Conference on Formal Methods in Software Engineering (FormaliSE)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124214750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1