2022 IEEE 31st Asian Test Symposium (ATS)最新文献

Enhanced Interconnect Test Method for Resistive Open Defects in Final Tests with Relaxation Oscillators 松弛振荡器最终试验中电阻性开口缺陷的增强互连试验方法

2022 IEEE 31st Asian Test Symposium (ATS) Pub Date : 2022-11-01 DOI: 10.1109/ATS56056.2022.00021

Masao Ohmatsu, Yuto Ohtera, Yuki Ikiri, H. Yotsuyanagi, Shyue-Kung Lu, M. Hashizume

引用次数: 0

Two-Dimensional Test Generation Objective 二维测试生成目标

2022 IEEE 31st Asian Test Symposium (ATS) Pub Date : 2022-11-01 DOI: 10.1109/ATS56056.2022.00031

I. Pomeranz

{"title":"Two-Dimensional Test Generation Objective","authors":"I. Pomeranz","doi":"10.1109/ATS56056.2022.00031","DOIUrl":"https://doi.org/10.1109/ATS56056.2022.00031","url":null,"abstract":"Test sets that target several fault models are important for addressing the need to achieve comprehensive defect coverage. A commonly used test generation process tops off the test set to address the fault models one by one. However, if the test set becomes excessively large, the order by which the fault models are targeted creates a bias in their fault coverages. This article considers the scenario where (1) a bound on the number of tests is introduced in advance, and (2) after targeting a fault model $F_{0}$, the detection of faults from fault models $F_{1}$ and $F_{2}$ is equally important for improving the quality of the test set. The article introduces a test generation objective that balances the detection of faults from $F_{1}$ and $F_{2}$ to reduce the bias toward one of them. It then describes a test generation procedure that uses the objective to produce a balanced test set in the case where a compressed test set for $F_{0}$ (consisting of single stuck-at faults) is used for producing all the tests for $F_{1}$ and $F_{2}$ (consisting of single-cycle gate-exhaustive faults and bridging faults, respectively). Experimental results for benchmark circuits are presented to support the discussion.","PeriodicalId":111107,"journal":{"name":"2022 IEEE 31st Asian Test Symposium (ATS)","volume":"81 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124710314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

PointerChecker: Tag-Based and Hardware-Assisted Memory Safety against Memory Corruption 指针检查器:基于标签和硬件辅助的防止内存损坏的内存安全

2022 IEEE 31st Asian Test Symposium (ATS) Pub Date : 2022-11-01 DOI: 10.1109/ATS56056.2022.00029

Xiaofan Nie, Liwei Chen, Gang Shi

{"title":"PointerChecker: Tag-Based and Hardware-Assisted Memory Safety against Memory Corruption","authors":"Xiaofan Nie, Liwei Chen, Gang Shi","doi":"10.1109/ATS56056.2022.00029","DOIUrl":"https://doi.org/10.1109/ATS56056.2022.00029","url":null,"abstract":"The exploitation of memory corruption continues to be a major threat to computer software and systems. Enforcing memory safety can stop all memory corruption exploits. Unfortu-nately, existing approaches for memory safety either suffer from high-performance overhead or have poor source compatibility. A compromise is only to detect spatial violations to get a trade-off between performance and security. However, temporal violations are still preferably targeted with the improvement of boundary checks. In this paper, we propose a lightweight solution, called PointerChecker, a complete memory safety architecture based on tagged memory. We design a 2-bit tag to represent four different memory states to protect both spatial and temporal safety. Besides, we design tag-based pointer metadata representations to reduce the storage of pointer metadata and the overhead of runtime checking. Combining them, we can successfully identify the memory safety violations at runtime. Based on LLVM infrastructure and LowRISC architecture, we implement the prototype with lightweight hardware extensions. The evaluation results show that the average performance overhead is 8.42%, and PointerChecker can provide source compatibility and strong security.","PeriodicalId":111107,"journal":{"name":"2022 IEEE 31st Asian Test Symposium (ATS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129679561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Radiation-Hardened Non-Volatile Magnetic Latch with High Reliability and Persistent Storage 具有高可靠性和持久存储的抗辐射非易失性磁闩锁

2022 IEEE 31st Asian Test Symposium (ATS) Pub Date : 2022-11-01 DOI: 10.1109/ATS56056.2022.00013

Aibin Yan, L. Ding, Zhen Zhou, Zhengfeng Huang, Jie Cui, P. Girard, X. Wen

引用次数: 1

Organizing Committee: ATS 2022 组委会:ATS 2022

2022 IEEE 31st Asian Test Symposium (ATS) Pub Date : 2022-11-01 DOI: 10.1109/ats56056.2022.00006

引用次数: 0

Using Formal Methods to Support the Development of STLs for GPUs 使用形式化方法支持gpu的stl开发

2022 IEEE 31st Asian Test Symposium (ATS) Pub Date : 2022-11-01 DOI: 10.1109/ATS56056.2022.00027

N. I. Deligiannis, Tobias Faller, J. E. R. Condia, R. Cantoro, B. Becker, M. Reorda

{"title":"Using Formal Methods to Support the Development of STLs for GPUs","authors":"N. I. Deligiannis, Tobias Faller, J. E. R. Condia, R. Cantoro, B. Becker, M. Reorda","doi":"10.1109/ATS56056.2022.00027","DOIUrl":"https://doi.org/10.1109/ATS56056.2022.00027","url":null,"abstract":"Graphics Processing Units (GPUs) boost the development of high-performance safety-critical applications. The reliability of such systems is of utmost importance since faults affecting the hardware may occur at any time during the systems' operational life. Thus, methods to effectively test these devices during their in-field operation are necessary. One popular solution relies on Software Test Libraries (STLs), which recently have been started being used for G PU s as well, since they are effective in terms of fault detection capabilities, intrusiveness, flexibility, and test duration. A drawback of the STL approach for G PU s is the extensive effort used to develop effective test routines for complex structures, e.g., controllers, due to the complicated constraints stemming from the ISA, the available compilation flows and parallelism constraints. We propose a novel technique based on formal methods to support the generation of stimuli and enhance the quality of pre-existing STLs for GPUs. To validate the proposed method, we resort to an open-source GPU model (Flex GripPlu s). Experimental results show that the method can effectively generate complementary code fragments to be added to existing STLs and increase their fault coverage. In the case of the GPU's decoding unit, the stuck-at fault coverage was increased by nearly 10%.","PeriodicalId":111107,"journal":{"name":"2022 IEEE 31st Asian Test Symposium (ATS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134018479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Selecting Path Delay Faults Through the Largest Subcircuits of Uncovered Lines 通过未覆盖线路的最大子电路选择路径延迟故障

2022 IEEE 31st Asian Test Symposium (ATS) Pub Date : 2022-11-01 DOI: 10.1109/ATS56056.2022.00032

I. Pomeranz

引用次数: 0

Locating Critical-Reliability Gates for Sequential Circuits based on the Time Window Graph Model 基于时间窗图模型的顺序电路临界可靠性门定位

2022 IEEE 31st Asian Test Symposium (ATS) Pub Date : 2022-11-01 DOI: 10.1109/ATS56056.2022.00014

Weidong Zhu, Jianhui Jiang, Zhanhui Shi

{"title":"Locating Critical-Reliability Gates for Sequential Circuits based on the Time Window Graph Model","authors":"Weidong Zhu, Jianhui Jiang, Zhanhui Shi","doi":"10.1109/ATS56056.2022.00014","DOIUrl":"https://doi.org/10.1109/ATS56056.2022.00014","url":null,"abstract":"The dependability of systems gains extensive attention as they are vulnerable to unexpected events, such as soft errors in circuits. Many works proposed to enhance the reliability of circuits at a low cost by hardening the reliability-critical gates (RCGs). However, it is challenging and necessary to determine the gates that need to be improved, especially for sequential circuits. Currently, methods used to locate RCGs for sequential circuits are struggling to balance the accuracy and computational overhead. This paper presents a method for locating RCGs of sequential circuits, the states of gates are aggregated into slices based on the time window graph model, then a probability-based calculation method is proposed for quantifying the criticality of gate reliability oriented to slices, finally, locating RCGs for sequential circuits which takes the accumulation of faults into consideration. Experiments on fifty ISCAS-89 and six ITC-99 benchmark circuits show that, on average, the accuracy of our method is 0.9417 of that of Monte Carlo (MC) method, and the speed and memory cost are 1725 times faster and 5.57 times lower than those of MC method. In addition, the proposed method is much faster and more accurate than stochastic method for large-scale circuits.","PeriodicalId":111107,"journal":{"name":"2022 IEEE 31st Asian Test Symposium (ATS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115238113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Using Hopfield Networks to Correct Instruction Faults 利用Hopfield网络纠正指令故障

2022 IEEE 31st Asian Test Symposium (ATS) Pub Date : 2022-11-01 DOI: 10.1109/ATS56056.2022.00030

Troya Çağıl Köylü, M. Fieback, S. Hamdioui, M. Taouil

引用次数: 1

On Correction of A Delay Value Using Ring-Oscillators for Aging Detection and Prediction 用环振器校正延迟值用于老化检测和预测

2022 IEEE 31st Asian Test Symposium (ATS) Pub Date : 2022-11-01 DOI: 10.1109/ATS56056.2022.00023

Takaaki Kato, Yousuke Miyake, S. Kajihara

{"title":"On Correction of A Delay Value Using Ring-Oscillators for Aging Detection and Prediction","authors":"Takaaki Kato, Yousuke Miyake, S. Kajihara","doi":"10.1109/ATS56056.2022.00023","DOIUrl":"https://doi.org/10.1109/ATS56056.2022.00023","url":null,"abstract":"On-chip delay measurement in field is effective for aging detection and prediction of a logic circuit. On the other hand, circuit delay is affected by not only aging but also environment such as temperature and voltage. When comparing a value of measured circuit delay with another value measured in different time to check the progress of aging, we need to correct the measured delay value to allow a fair comparison by eliminating the influence of environmental variations from the delay values. In this paper, we propose a method to convert circuit delay values measured in field into ones measured under the same environment i.e., predetermined temperature and voltage condition. The proposed method, which employs a digital temperature and voltage sensor with ring-oscillators, uses not temperature and voltage values but ROs frequency in the sensor. Furthermore, we also introduce a calibration method for reducing correction errors due to process variation. In evaluation for TEG chips in 65nm CMOS process, the proposed method can improve the correction accuracy for from 83.91ps to 39.78ps. The corrected delay values correspond to 317-day of aging and the prediction accuracy improves 48-day compared with correction using temperature and voltage values.","PeriodicalId":111107,"journal":{"name":"2022 IEEE 31st Asian Test Symposium (ATS)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128321499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0