Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154)最新文献

Supporting integrated services in wireless networks with space-time block-coded transmissions 支持时空分组编码传输的无线网络综合业务

Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154) Pub Date : 2000-12-01 DOI: 10.1109/ACSSC.2000.910763

Zhiqiang Liu, A. Stamoulis, G. Giannakis

引用次数: 2

Iterative decoding of space-time trellis codes and related implementation issues 时空网格码的迭代译码及其实现问题

Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154) Pub Date : 2000-12-01 DOI: 10.1109/ACSSC.2000.911018

Z. Chi, Zhongfeng Wang, K. Parhi

引用次数: 7

A fast constant modulus algorithm for blind equalization 一种快速恒模盲均衡算法

Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154) Pub Date : 2000-12-01 DOI: 10.1109/ACSSC.2000.910666

S. Nelatury, Sathyanarayan S. Rao

引用次数: 0

Coordinated training and transmission for improved interference cancellation in a cellular network 蜂窝网络中用于改进干扰消除的协调训练和传输

Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154) Pub Date : 2000-12-01 DOI: 10.1109/ACSSC.2000.910652

R. Heath, J. Tellado, S.K. Peroor, A. Paulraj

引用次数: 1

Adaptive error-cancellation for low-power digital filtering 低功耗数字滤波的自适应误差抵消

Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154) Pub Date : 2000-12-01 DOI: 10.1109/ACSSC.2000.911279

Lei Wang, N. Shanbhag

引用次数: 2

VLIW DSP vs. superscalar implementation of a baseline 11.263 video encoder VLIW DSP与基线11.263视频编码器的超标量实现

Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154) Pub Date : 2000-12-01 DOI: 10.1109/ACSSC.2000.911272

S. Banerjee, H. Sheikh, L. John, B. Evans, A. Bovik

{"title":"VLIW DSP vs. superscalar implementation of a baseline 11.263 video encoder","authors":"S. Banerjee, H. Sheikh, L. John, B. Evans, A. Bovik","doi":"10.1109/ACSSC.2000.911272","DOIUrl":"https://doi.org/10.1109/ACSSC.2000.911272","url":null,"abstract":"A Very Long Instruction Word (VLIW) processor and a superscalar processor can execute multiple instructions simultaneously. A VLIW processor depends on the compiler and programmer to find the parallelism in the instructions, whereas a superscaler processor determines the parallelism at runtime. This paper compares TI TMS320C6700 VLIW digital signal processor (DSP) and SimpleScalar superscalar implementations of a baseline 11.263 video encoder in C. With level two C compiler optimization, a one-way issue superscalar processor is 7.5 times faster than the VLIW DSP for the same processor clock speed. The superscalar speedup from one-way to four-way issue is 2.88:1, and from four-way to 256-way issue is 2.43:1. To reduce the execution time on the C6700, we write assembly routines for sum-of-absolute-difference, interpolation, and reconstruction, and place frequently used code and data into on-chip memory. We use TI's discrete cosine transform assembly routines. The hand optimized VLIW DSP implementation is 61/spl times/ faster than the C version compiled with level two optimization. Most of the improvement was due to the efficient placement of data and programs in memory. The hand optimized VLIW implementation is 14% faster than a 256-way superscalar implementation without hand optimizations.","PeriodicalId":10581,"journal":{"name":"Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154)","volume":"92 1","pages":"1665-1669 vol.2"},"PeriodicalIF":0.0,"publicationDate":"2000-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82683103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

A signal separation algorithm for fetal heart-rate estimation 胎儿心率估计的信号分离算法

Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154) Pub Date : 2000-12-01 DOI: 10.1109/ACSSC.2000.910976

Kuei-Chiang Lai, J. Shynk

引用次数: 4

Generalized lapped biorthogonal transforms using lifting steps 使用提升步骤的广义重叠双正交变换

Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154) Pub Date : 2000-12-01 DOI: 10.1109/ACSSC.2000.910944

M. Kawada, M. Ikehara

引用次数: 0

Linear unitary precoders for maximum diversity gains with multiple transmit and receive antennas 具有多个发射和接收天线的最大分集增益的线性统一预编码器

Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154) Pub Date : 2000-12-01 DOI: 10.1109/ACSSC.2000.911250

Yan Xin, Zhengdao Wang, G. Giannakis

引用次数: 28

Performance of ML rate determination for an IS-95 downlink SIC receiver IS-95下行SIC接收机的ML速率测定性能

Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154) Pub Date : 2000-12-01 DOI: 10.1109/ACSSC.2000.910655

R. Cagley, Kuei-Chiang Lai, J. Shynk

{"title":"Performance of ML rate determination for an IS-95 downlink SIC receiver","authors":"R. Cagley, Kuei-Chiang Lai, J. Shynk","doi":"10.1109/ACSSC.2000.910655","DOIUrl":"https://doi.org/10.1109/ACSSC.2000.910655","url":null,"abstract":"Maximum likelihood (ML) decision rules, such as that presented by Gutierrez, Lee and Mandyam (see. Proc. IEEE 49th Vehicular Technology Conf., Houston, TX, p.417-21, 1999), can be used for rate determination in an IS-95 system to reduce the complexity of the Viterbi decoder. We extend this previous work by determining whether it is beneficial to use rate determination for the successive interference canceller (SIC) in an IS-95 downlink receiver. Assuming certain conditions are met regarding the signal-to-noise ratio (SNR) and the number of received symbols used for rate determination, employing knowledge of bit repetition can decrease the bit error rare (BER) for the corresponding Walsh channels. To further increase the effectiveness of interference cancellation, soft decision decoding can be used instead of a conventional hard decision device. The devices considered here are similar to those of Frey and Reinhardt (see Proc. IEEE 47th Vehicular Technology Conf., Phoenix, AZ, p.155-159, 1997), but they use the knowledge that there can be repeated bits in the IS-95 downlink.","PeriodicalId":10581,"journal":{"name":"Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154)","volume":"142 1","pages":"956-959 vol.2"},"PeriodicalIF":0.0,"publicationDate":"2000-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81747652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2