2020 Formal Methods in Computer Aided Design (FMCAD)最新文献_第3页

Thread-modular Counter Abstraction for Parameterized Program Safety 参数化程序安全的线程模块化计数器抽象

2020 Formal Methods in Computer Aided Design (FMCAD) Pub Date : 2020-09-21 DOI: 10.34727/2020/isbn.978-3-85448-042-6_13

Thomas Pani, Georg Weissenbacher, Florian Zuleger

引用次数: 0

Model Checking Software-Defined Networks with Flow Entries that Time Out 具有超时流项的软件定义网络的模型检查

2020 Formal Methods in Computer Aided Design (FMCAD) Pub Date : 2020-08-14 DOI: 10.34727/2020/isbn.978-3-85448-042-6_25

Vasileios Klimis, G. Parisis, Bernhard Reus

{"title":"Model Checking Software-Defined Networks with Flow Entries that Time Out","authors":"Vasileios Klimis, G. Parisis, Bernhard Reus","doi":"10.34727/2020/isbn.978-3-85448-042-6_25","DOIUrl":"https://doi.org/10.34727/2020/isbn.978-3-85448-042-6_25","url":null,"abstract":"Software-defined networking (SDN) enables advanced operation and management of network deployments through (virtually) centralised, programmable controllers, which deploy network functionality by installing rules in the flow tables of network switches. Although this is a powerful abstraction, buggy controller functionality could lead to severe service disruption and security loopholes, motivating the need for (semi-)automated tools to find, or even verify absence of, bugs. Model checking SDNs has been proposed in the literature, but none of the existing approaches can support dynamic network deployments, where flow entries expire due to timeouts. This is necessary for automatically refreshing (and eliminating stale) state in the network (termed as soft-state in the network protocol design nomenclature), which is important for scaling up applications or recovering from failures. In this paper, we extend our model (MoCS) to deal with timeouts of flow table entries, thus supporting soft state in the network. Optimisations are proposed that are tailored to this extension. We evaluate the performance of the proposed model in Uppaal using a load balancer and firewall in network topologies of varying size.","PeriodicalId":105705,"journal":{"name":"2020 Formal Methods in Computer Aided Design (FMCAD)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128728684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Reactive Synthesis from Extended Bounded Response LTL Specifications 扩展有界响应LTL规范的反应性合成

2020 Formal Methods in Computer Aided Design (FMCAD) Pub Date : 2020-08-12 DOI: 10.34727/2020/isbn.978-3-85448-042-6_15

A. Cimatti, Luca Geatti, N. Gigante, A. Montanari, Stefano Tonetta

引用次数: 6

Switss: Computing Small Witnessing Subsystems 瑞士:计算小型见证子系统

2020 Formal Methods in Computer Aided Design (FMCAD) Pub Date : 2020-08-10 DOI: 10.34727/2020/isbn.978-3-85448-042-6_31

Simon Jantsch, Hans Harder, Florian Funke, C. Baier

引用次数: 1

Trace Logic for Inductive Loop Reasoning 跟踪逻辑的归纳回路推理

2020 Formal Methods in Computer Aided Design (FMCAD) Pub Date : 2020-08-04 DOI: 10.34727/2020/isbn.978-3-85448-042-6_33

Pamina Georgiou, Bernhard Gleiss, Laura Kov'acs

引用次数: 10

Angelic Checking within Static Driver Verifier: Towards high-precision defects without (modeling) cost 静态驱动验证器内的天使检查:无(建模)成本的高精度缺陷

2020 Formal Methods in Computer Aided Design (FMCAD) Pub Date : 2020-07-01 DOI: 10.34727/2020/isbn.978-3-85448-042-6_24

Shuvendu K. Lahiri, A. Lal, S. Gopinath, Alexander Nutz, V. Levin, Rahul Kumar, Nate Deisinger, J. Lichtenberg, Chetan Bansal

{"title":"Angelic Checking within Static Driver Verifier: Towards high-precision defects without (modeling) cost","authors":"Shuvendu K. Lahiri, A. Lal, S. Gopinath, Alexander Nutz, V. Levin, Rahul Kumar, Nate Deisinger, J. Lichtenberg, Chetan Bansal","doi":"10.34727/2020/isbn.978-3-85448-042-6_24","DOIUrl":"https://doi.org/10.34727/2020/isbn.978-3-85448-042-6_24","url":null,"abstract":"Microsoft's Static Driver Verifier (SDV) pioneered the use of software model checking for ensuring that device drivers correctly use operating system (OS) APIs. However, the verification methodology has been difficult to extend in order to support either (a) new classes of drivers for which SDV does not already have a harness and stubs, or (b) memory-corruption properties. Any attempt to apply SDV out-of-the-box results in either false alarms due to the lack of environment modeling, or scalability issues when finding deeply nested bugs in the presence of a very large number of memory accesses. In this paper, we describe our experience designing and shipping a new class of checks known as angelic checks through SDV with the aid of angelic verification (AV) [1] technology, over a period of 4 years. AV pairs a precise inter-procedural assertion checker with automatic inference of likely specifications for the environment. AV helps compensate for the lack of environment modeling and regains scalability by making it possible to find deeply nested bugs, even for complex memory-corruption properties. These new rules have together found over a hundred confirmed defects during internal deployment at Microsoft, including several previously unknown high-impact potential security vulnerabilities. AV considerably increases the reach of SDV, both in terms of drivers as well as rules that it can support effectively.","PeriodicalId":105705,"journal":{"name":"2020 Formal Methods in Computer Aided Design (FMCAD)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132995702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A Theoretical Framework for Symbolic Quick Error Detection 符号快速错误检测的理论框架

2020 Formal Methods in Computer Aided Design (FMCAD) Pub Date : 2020-06-09 DOI: 10.34727/2020/isbn.978-3-85448-042-6_9

Florian Lonsing, S. Mitra, Clark W. Barrett

{"title":"A Theoretical Framework for Symbolic Quick Error Detection","authors":"Florian Lonsing, S. Mitra, Clark W. Barrett","doi":"10.34727/2020/isbn.978-3-85448-042-6_9","DOIUrl":"https://doi.org/10.34727/2020/isbn.978-3-85448-042-6_9","url":null,"abstract":"Symbolic quick error detection (SQED) is a formal pre-silicon verification technique targeted at processor designs. It leverages bounded model checking (BMC) to check a design for counterexamples to a self-consistency property: given the instruction set architecture (ISA) of the design, executing an instruction sequence twice on the same inputs must always produce the same outputs. Self-consistency is a universal, implementation-independent property. Consequently, in contrast to traditional verification approaches that use implementation-specific assertions (often generated manually), SQED does not require a full formal design specification or manually-written properties. Case studies have shown that SQED is effective for commercial designs and that SQED substantially improves design productivity. However, until now there has been no formal characterization of its bug-finding capabilities. We aim to close this gap by laying a formal foundation for SQED. We use a transition-system processor model and define the notion of a bug using an abstract specification relation. We prove the soundness of SQED, i.e., that any bug reported by SQED is in fact a real bug in the processor. Importantly, this result holds regardless of what the actual specification relation is. We next describe conditions under which SQED is complete, that is, what kinds of bugs it is guaranteed to find. We show that for a large class of bugs, SQED can always find a trace exhibiting the bug. Ultimately, we prove full completeness of a variant of SQED that uses specialized state reset instructions. Our results enable a rigorous understanding of SQED and its bug-finding capabilities and give insights on how to optimize implementations of SQED in practice.","PeriodicalId":105705,"journal":{"name":"2020 Formal Methods in Computer Aided Design (FMCAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131519772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Formal Methods with a Touch of Magic 具有魔力的形式化方法

2020 Formal Methods in Computer Aided Design (FMCAD) Pub Date : 2020-05-25 DOI: 10.34727/2020/isbn.978-3-85448-042-6_21

Parand Alizadeh Alamdari, Guy Avni, T. Henzinger, Anna Lukina

引用次数: 10

Parallelization Techniques for Verifying Neural Networks 验证神经网络的并行化技术

2020 Formal Methods in Computer Aided Design (FMCAD) Pub Date : 2020-04-17 DOI: 10.34727/2020/isbn.978-3-85448-042-6_20

Haoze Wu, Alex Ozdemir, Aleksandar Zeljić, A. Irfan, Kyle D. Julian, D. Gopinath, Sadjad Fouladi, Guy Katz, C. Pasareanu, Clark W. Barrett

引用次数: 47

Art: Abstraction Refinement-Guided Training for Provably Correct Neural Networks 艺术:抽象提炼指导训练可证明正确的神经网络

2020 Formal Methods in Computer Aided Design (FMCAD) Pub Date : 2019-07-17 DOI: 10.34727/2020/isbn.978-3-85448-042-6_22

Xuankang Lin, He Zhu, R. Samanta, S. Jagannathan

{"title":"Art: Abstraction Refinement-Guided Training for Provably Correct Neural Networks","authors":"Xuankang Lin, He Zhu, R. Samanta, S. Jagannathan","doi":"10.34727/2020/isbn.978-3-85448-042-6_22","DOIUrl":"https://doi.org/10.34727/2020/isbn.978-3-85448-042-6_22","url":null,"abstract":"Artificial Neural Networks (ANNs) have demonstrated remarkable utility in various challenging machine learning applications. While formally verified properties of their behaviors are highly desired, they have proven notoriously difficult to derive and enforce. Existing approaches typically formulate this problem as a post facto analysis process. In this paper, we present a novel learning framework that ensures such formal guarantees are enforced by construction. Our technique enables training provably correct networks with respect to a broad class of safety properties, a capability that goes well-beyond existing approaches, without compromising much accuracy. Our key insight is that we can integrate an optimization-based abstraction refinement loop into the learning process and operate over dynamically constructed partitions of the input space that considers accuracy and safety objectives synergistically. The refinement procedure iteratively splits the input space from which training data is drawn, guided by the efficacy with which such partitions enable safety verification. We have implemented our approach in a tool (ART) and applied it to enforce general safety properties on unmanned aviator collision avoidance system ACAS Xu dataset and the Collision Detection dataset. Importantly, we empirically demonstrate that realizing safety does not come at the price of much accuracy. Our methodology demonstrates that an abstraction refinement methodology provides a meaningful pathway for building both accurate and correct machine learning networks.","PeriodicalId":105705,"journal":{"name":"2020 Formal Methods in Computer Aided Design (FMCAD)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122981065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 22