2001 IEEE International Symposium on Performance Analysis of Systems and Software. ISPASS.最新文献

Automatic memory hierarchy characterization 自动记忆层次表征

2001 IEEE International Symposium on Performance Analysis of Systems and Software. ISPASS. Pub Date : 2001-11-04 DOI: 10.1109/ISPASS.2001.990684

Clark L. Coleman, J. Davidson

{"title":"Automatic memory hierarchy characterization","authors":"Clark L. Coleman, J. Davidson","doi":"10.1109/ISPASS.2001.990684","DOIUrl":"https://doi.org/10.1109/ISPASS.2001.990684","url":null,"abstract":"As the gap between memory speed and processor speed grows, program transformations to improve the peflormance of the memory system have become increasingly important. To understand and optimize memory performance, researchers and practitioners in performance analysis and compiler design require a detailed understanding of the memory hierarchy of the target computer system. Unfortunately, accurate information about the memory hierarchy is not easy to obtain. Vendor microprocessor documentation is ofen incomplete, vague, or worse, erroneous in its description of important on-chip memory parameters. Furthermore, today S computer systems contain complex, multi-level memory systems where the processor is but one component of the memory system. The accuracy of the documentation on the complete memory system is also lacking. This paper describes the implementation of a portable program that automatically determines all of a computer system’s important memory hierarchy parameters. Automatic determination of memory hierarchy parameters is shown to be superior to reliance on vendor data. The robustness and portability of the approach is demonstrated by determining and validating the memory hierarchy parameters for a number of different computer systems, using several of the emerging performance counter application programming inte$aces.","PeriodicalId":104148,"journal":{"name":"2001 IEEE International Symposium on Performance Analysis of Systems and Software. ISPASS.","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126454967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

Statistical usage testing applied to mobile network verification 统计使用测试应用于移动网络验证

2001 IEEE International Symposium on Performance Analysis of Systems and Software. ISPASS. Pub Date : 2001-11-04 DOI: 10.1109/ISPASS.2001.990694

A. Ost, Dorien van Logchem

引用次数: 1

An evaluation of search tree techniques in the presence of caches 对存在缓存的搜索树技术的评价

2001 IEEE International Symposium on Performance Analysis of Systems and Software. ISPASS. Pub Date : 2001-11-04 DOI: 10.1109/ISPASS.2001.990682

Costin Iancu, A. Acharya

{"title":"An evaluation of search tree techniques in the presence of caches","authors":"Costin Iancu, A. Acharya","doi":"10.1109/ISPASS.2001.990682","DOIUrl":"https://doi.org/10.1109/ISPASS.2001.990682","url":null,"abstract":"Two techniques underlie the design of commonly used search-tree algorithms: move commonly accessed items closer to the root (move-to-front) and keep the tree balanced (keep-it-balanced). The move-to-front technique tries to improve the performance for the common case by reducing the number of operations required to retrieve heavily accessed items. The keep-it-balanced technique tries to improve worst-case performance by reducing the maximum number of operations required to look up an item in the tree. In this paper, we evaluate these techniques in the presence of a cache hierarchy. As representatives of move-to-front algorithms we use splay trees. As representatives of keep-it-balanced algorithms we use B-Trees and B*-Trees. In addition to classic versions of these techniques, we evaluate variants that have been optimized for a cache hierarchy. To drive our evaluation, we use a suite of synthetic datasets. These data-sets vary primarily in the degree of locality found in the request stream and the operation mix. The major result of this paper is a qualitative performance difference analysis of the two classes of algorithms based on the expected data input characteristics. Based on this analysis, we can predict which algorithm performs faster for a large class of input data-sets. We also present guidelines for choosing implementation parameters in the presence of a cache hierarchy for all","PeriodicalId":104148,"journal":{"name":"2001 IEEE International Symposium on Performance Analysis of Systems and Software. ISPASS.","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127119275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Geist: a generator for e-commerce & internet server traffic Geist:电子商务和互联网服务器流量的生成器

2001 IEEE International Symposium on Performance Analysis of Systems and Software. ISPASS. Pub Date : 2001-11-04 DOI: 10.1109/ISPASS.2001.990676

K. Kant, V. Tewari, R. Iyer

引用次数: 29

The effects of context switching on branch predictor performance 上下文切换对分支预测器性能的影响

2001 IEEE International Symposium on Performance Analysis of Systems and Software. ISPASS. Pub Date : 2001-11-04 DOI: 10.1109/ISPASS.2001.990679

M. Co, K. Skadron

{"title":"The effects of context switching on branch predictor performance","authors":"M. Co, K. Skadron","doi":"10.1109/ISPASS.2001.990679","DOIUrl":"https://doi.org/10.1109/ISPASS.2001.990679","url":null,"abstract":"This paper shows that contezt switching is not a significant factor to be considered when performing general branch prediction studies. Branch prediction allows for speculative ezecution by increasing available instruction level parallelism (ILP) and hiding the time required to resolve branch conditions. Accurate simulation of branch prediction is important because bmnch prediction strongly influences the behavior of processor structures. For this study, a timesharing framework was developed by modifying SimpleScalar 's branch predictor simulator. A thorough characterization of the effects of branch predictor configumtion, branch predictor area, and time slice length is provided. As further verification, branch predictor performance with and without flushing the predictor structures is compared. Ezperiments show that operating system wntezt switches have little effect on branch prediction rate when using time slices representative of today's operating systems. Our findings show that this results from the fact that time slices are much larger than the training time required by the bmnch predictor structures. For all predictor configurations tested, the predictors train in under l28K instructions with o r without flushing the branch predictor structures.","PeriodicalId":104148,"journal":{"name":"2001 IEEE International Symposium on Performance Analysis of Systems and Software. ISPASS.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117024368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

Understanding control flow transfer and its predictability in java processing 理解java处理中的控制流转移及其可预测性

2001 IEEE International Symposium on Performance Analysis of Systems and Software. ISPASS. Pub Date : 2001-11-04 DOI: 10.1109/ISPASS.2001.990678

Tao Li, L. John

{"title":"Understanding control flow transfer and its predictability in java processing","authors":"Tao Li, L. John","doi":"10.1109/ISPASS.2001.990678","DOIUrl":"https://doi.org/10.1109/ISPASS.2001.990678","url":null,"abstract":"An in-depth look and understanding of control flow transfer arid its predictability can guide architects to adapt control flow prediction hardware in Java processing or finely tune the performance of JVM sojhare.on general purpose machines. To our knowledge, this paper provides the first insight of branch behavior on a standard Java Virtual Machine with real workloads. Employing a complete system simulation environment, we profile brunch execution characteristics and quantify the performance of a wide range of prediction schemes on both user and kernel code. The impact of different JVM styles (JIT compiler and interpreter) on branch behavior is also studied. We firid that: (I) Kernel branches constitute a significant portion of total branch execution in Java processing; (2) Kernel and user code favor different prediction mechanisms; (3) Java processing exercises fairly large number of branch sites and large control flow footprint compared with the execution of benchmarks such us SPEClnt95; (4) A major part of the dynamic indirect branches are multiple target (polymorphic) brunches. Target addresses of indirect branches, especially those in interpreting mode are highly interleaved and cause high BTB tiiisprediction.","PeriodicalId":104148,"journal":{"name":"2001 IEEE International Symposium on Performance Analysis of Systems and Software. ISPASS.","volume":"58 S2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114093684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Early design phase power/performance modeling through statistical simulation 通过统计仿真进行早期设计阶段功率/性能建模

2001 IEEE International Symposium on Performance Analysis of Systems and Software. ISPASS. Pub Date : 2001-11-04 DOI: 10.1109/ISPASS.2001.990669

L. Eeckhout, K. D. Bosschere

引用次数: 27

Using program and user information to improve file prediction performance 利用程序和用户信息提高文件预测性能

2001 IEEE International Symposium on Performance Analysis of Systems and Software. ISPASS. Pub Date : 2001-11-04 DOI: 10.1109/ISPASS.2001.990685

Tsozen Yeh, D. Long, S. Brandt

引用次数: 14

About the sensitivity of the HLRC-DU protocol on diff and page sizes 关于HLRC-DU协议对差异和页面大小的敏感性

2001 IEEE International Symposium on Performance Analysis of Systems and Software. ISPASS. Pub Date : 2001-11-04 DOI: 10.1109/ISPASS.2001.990675

S. Petit, J. Sahuquillo, A. Pont

引用次数: 3

Estimating internal memory fragmentation for java programs under the binary buddy policy 估计在二进制伙伴策略下java程序的内部内存碎片

2001 IEEE International Symposium on Performance Analysis of Systems and Software. ISPASS. Pub Date : 2001-11-04 DOI: 10.1109/ISPASS.2001.990681

Therapon Skotiniotis, J. M. Chang

引用次数: 1