2021 IEEE Workshop on Signal Processing Systems (SiPS)最新文献_第5页

Low-Latency Parallel Hermitian Positive-Definite Matrix Inversion for Massive MIMO 大规模MIMO的低延迟并行厄米正定矩阵反演

2021 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2021-10-01 DOI: 10.1109/SiPS52927.2021.00013

Erik Bertilsson, Carl Ingemarsson, O. Gustafsson

引用次数: 0

Computationally-efficient voice activity detection based on deep neural networks 基于深度神经网络的高效计算语音活动检测

2021 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2021-10-01 DOI: 10.1109/SiPS52927.2021.00020

Yan Xiong, Visar Berisha, C. Chakrabarti

引用次数: 1

Efficient Mind-wandering Detection System with GSR Signals on MM-SART Database 基于MM-SART数据库的GSR信号高效走神检测系统

2021 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2021-10-01 DOI: 10.1109/SiPS52927.2021.00043

Sheng Chang, Yi-Ta Chen, A. Wu

{"title":"Efficient Mind-wandering Detection System with GSR Signals on MM-SART Database","authors":"Sheng Chang, Yi-Ta Chen, A. Wu","doi":"10.1109/SiPS52927.2021.00043","DOIUrl":"https://doi.org/10.1109/SiPS52927.2021.00043","url":null,"abstract":"Mind-wandering (MW) is a ubiquitous phenomenon where the attention involuntary shifts from task-related to task-unrelated thoughts, and thus MW has negative impacts on task performance during learning. In this paper, we propose a MW detection system with galvanic skin response (GSR) signals on the multi-modal for Sustained Attention to Response Task (MM-SART) database. To explore the relationships between GSR and MW, we extract total 119 features including time, frequency, entropy, and wavelet domain. By using XGBoost as the classifier, we can achieve 0.713 AUC on the MM-SART database. However, large number of features may cause high training complexity and long inference latency. To reduce the number of features and find the most dominant features related to MW, we apply Pearson’s correlation coefficients and the importance scores given by extreme gradient boosting (XGBoost) classifier. Experiment results show that by using 10 dominant features we can achieve 0.706 AUC, 70.3% accuracy, 70.8% weighted F1 score and 0.294 Cohen’s kappa score on the MM-SART database. Moreover, the latency of training and inference are significantly reduced by 5x and 184x respectively. In conclusion, we have proposed an efficient MW detection system with GSR signals on the MM-SART database.","PeriodicalId":103894,"journal":{"name":"2021 IEEE Workshop on Signal Processing Systems (SiPS)","volume":"279 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114430937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Efficient Architecture for Long Integer Modular Multiplication over Solinas Prime Solinas素数上长整数模乘法的有效结构

2021 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2021-10-01 DOI: 10.1109/SiPS52927.2021.00034

Zheang Huai, K. Parhi, Xinmiao Zhang

{"title":"Efficient Architecture for Long Integer Modular Multiplication over Solinas Prime","authors":"Zheang Huai, K. Parhi, Xinmiao Zhang","doi":"10.1109/SiPS52927.2021.00034","DOIUrl":"https://doi.org/10.1109/SiPS52927.2021.00034","url":null,"abstract":"Modular multiplication of very long integers is a key building block of fully homomorphic encryption and elliptic curve cryptography. The Karatsuba algorithm reduces the multiplication complexity by decomposing the operands into shorter segments. However, in the case of long numbers, adding up the segment products to derive the final product and then carrying out modular reduction as in previous designs can take many clock cycles. This paper focuses on moduli in the format of Solinas prime and proposes to integrate modular reduction into every segment product of the Karatsuba integer multiplication. As a result, the length of the intermediate results is further reduced and they can be added up simultaneously by using a carry-save adder at the cost of small area increase. Additionally, the computation scheduling are optimized to reduce the required number of registers and multiplexers. Complexity analysis shows that, for decomposition factors of 2, 3 and 4, our design requires on average 18.5% less clock cycles with only 5.9% area overhead and similar critical path compared to carrying out the modular reduction on the final product.","PeriodicalId":103894,"journal":{"name":"2021 IEEE Workshop on Signal Processing Systems (SiPS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122003284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Leveraging Transprecision Computing for Machine Vision Applications at the Edge 利用透明计算的边缘机器视觉应用

2021 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2021-08-29 DOI: 10.1109/SiPS52927.2021.00044

U. Minhas, L. Mukhanov, G. Karakonstantis, H. Vandierendonck, R. Woods

引用次数: 4

High-Throughput VLSI Architecture for GRAND Markov Order 大马尔可夫阶的高吞吐量VLSI架构

2021 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2021-08-28 DOI: 10.1109/SiPS52927.2021.00036

Syed Mohsin Abbas, Marwan Jalaleddine, W. Gross

{"title":"High-Throughput VLSI Architecture for GRAND Markov Order","authors":"Syed Mohsin Abbas, Marwan Jalaleddine, W. Gross","doi":"10.1109/SiPS52927.2021.00036","DOIUrl":"https://doi.org/10.1109/SiPS52927.2021.00036","url":null,"abstract":"Guessing Random Additive Noise Decoding (GRAND) is a recently proposed Maximum Likelihood (ML) decoding technique. Irrespective of the structure of the error correcting code, GRAND tries to guess the noise that corrupted the codeword in order to decode any linear error-correcting block code. GRAND Markov Order (GRAND-MO) is a variant of GRAND that is useful to decode error correcting code transmitted over communication channels with memory which are vulnerable to burst noise. Usually, interleavers and de-interleavers are used in communication systems to mitigate the effects of channel memory. Interleaving and de-interleaving introduce undesirable latency, which increases with channel memory. To prevent this added latency penalty, GRAND-MO can be directly used on the hard demodulated channel signals. This work reports the first GRAND-MO hardware architecture which achieves an average throughput of up to 52 Gbps and 64 Gbps for a code length of 128 and 79 respectively. Compared to the GRANDAB, hard-input variant of GRAND, the proposed architecture achieves 3 dB gain in decoding performance for a target FER of 10−5. Similarly, comparing the GRAND-MO decoder with a decoder tailored for a (79,64) BCH code showed that the proposed architecture achieves 33% higher worst case throughput and 2 dB gain in decoding performance.","PeriodicalId":103894,"journal":{"name":"2021 IEEE Workshop on Signal Processing Systems (SiPS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114640233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Beam-Slicing for Jammer Mitigation in mmWave Massive MU-MIMO 毫米波大规模MU-MIMO中的波束切片干扰抑制

2021 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2021-08-06 DOI: 10.1109/SiPS52927.2021.00039

Oscar Castañeda, Gian Marti, Christoph Studer

引用次数: 1

Uplink Energy Efficiency of Cell-Free Massive MIMO With Transmit Power Control in Measured Propagation Channels 传输信道中具有发射功率控制的无小区大规模MIMO上行能量效率

2021 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2021-08-04 DOI: 10.1109/SiPS52927.2021.00037

Thomas Choi, Masaaki Ito, I. Kanno, Takeo Oseki, K. Yamazaki, A. Molisch

{"title":"Uplink Energy Efficiency of Cell-Free Massive MIMO With Transmit Power Control in Measured Propagation Channels","authors":"Thomas Choi, Masaaki Ito, I. Kanno, Takeo Oseki, K. Yamazaki, A. Molisch","doi":"10.1109/SiPS52927.2021.00037","DOIUrl":"https://doi.org/10.1109/SiPS52927.2021.00037","url":null,"abstract":"Cell-free massive MIMO (CF-mMIMO) is expected to provide reliable wireless services for a large number of user equipments (UEs) using access points (APs) distributed across a wide area. When the UEs are battery-powered, uplink energy efficiency (EE) becomes an important performance metric for CF-mMIMO systems. Therefore, if the \"target\" spectral efficiency (SE) is met, it is important to optimize the uplink EE when setting the transmit powers of the UEs. Also, such transmit power control (TPC) method must be tested on channel data from real-world measurements to prove its effectiveness. In this paper, we compare three different TPC algorithms using zero-forcing reception by applying them to 3.5 GHz channel measurement data featuring ∼30,000 possible AP locations and 8 UE locations in a 200m×200m area. We show that the max-min EE algorithm is highly effective in improving the uplink EE at a target SE, especially if the number of single-antenna APs is large, circuit power consumption is low, and the maximum allowed transmit power of the UEs is high.","PeriodicalId":103894,"journal":{"name":"2021 IEEE Workshop on Signal Processing Systems (SiPS)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133535012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Communication and Computation Reduction for Split Learning using Asynchronous Training 基于异步训练的分割学习通信与计算减少

2021 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2021-07-20 DOI: 10.1109/SiPS52927.2021.00022

Xing Chen, Jingtao Li, C. Chakrabarti

{"title":"Communication and Computation Reduction for Split Learning using Asynchronous Training","authors":"Xing Chen, Jingtao Li, C. Chakrabarti","doi":"10.1109/SiPS52927.2021.00022","DOIUrl":"https://doi.org/10.1109/SiPS52927.2021.00022","url":null,"abstract":"Split learning is a promising privacy-preserving distributed learning scheme that has low computation requirement at the edge device but has the disadvantage of high communication overhead between edge device and server. To reduce the communication overhead, this paper proposes a loss-based asynchronous training scheme that updates the client-side model less frequently and only sends/receives activations/gradients in selected epochs. To further reduce the communication over-head, the activations/gradients are quantized using 8-bit floating point prior to transmission. An added benefit of the proposed communication reduction method is that the computations at the client side are reduced due to reduction in the number of client model updates. Furthermore, the privacy of the proposed communication reduction based split learning method is almost the same as traditional split learning. Simulation results on VGG11, VGG13 and ResNet18 models on CIFAR-10 show that the communication cost is reduced by 1.64x-106.7x and the computations in the client are reduced by 2.86x-32.1x when the accuracy degradation is less than 0.5% for the single-client case. For 5 and 10-client cases, the communication cost reduction is 11.9x and 11.3x on VGG11 for 0.5% loss in accuracy.","PeriodicalId":103894,"journal":{"name":"2021 IEEE Workshop on Signal Processing Systems (SiPS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115667292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17

Implementing a LoRa Software-Defined Radio on a General-Purpose ULP Microcontroller 在通用ULP微控制器上实现LoRa软件定义无线电

2021 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2021-07-12 DOI: 10.1109/SiPS52927.2021.00027

Mathieu Xhonneux, J. Louveaux, D. Bol

{"title":"Implementing a LoRa Software-Defined Radio on a General-Purpose ULP Microcontroller","authors":"Mathieu Xhonneux, J. Louveaux, D. Bol","doi":"10.1109/SiPS52927.2021.00027","DOIUrl":"https://doi.org/10.1109/SiPS52927.2021.00027","url":null,"abstract":"Emerging Internet-of-Things sensing applications rely on ultra low-power (ULP) microcontroller units (MCUs) that wirelessly transmit data to the cloud. Typical MCUs nowadays consist of generic blocks, except for the protocol-specific radios implemented in hardware. Hardware radios however slow down the evolution of wireless protocols due to retrocompatiblity concerns. In this work, we explore a software-defined radio architecture by demonstrating a LoRa transceiver running on custom ULP MCU codenamed SleepRider with an ARM Cortex-M4 CPU. In SleepRider MCU, we offload the generic baseband operations (e.g., low-pass filtering) to a reconfigurable digital front-end block and use the Cortex-M4 CPU to perform the protocol-specific computations. Our software implementation of the LoRa physical layer only uses the native SIMD instructions of the Cortex-M4 to achieve real-time transmission and reception of LoRa packets. SleepRider MCU has been fabricated in a 28nm FDSOI CMOS technology and is used in a testbed to experimentally validate the software implementation. Experimental results show that the proposed software-defined radio requires only a CPU frequency of 20 MHz to correctly receive a LoRa packet, with an ultra-low power consumption of 0.42 mW on average.","PeriodicalId":103894,"journal":{"name":"2021 IEEE Workshop on Signal Processing Systems (SiPS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122784261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5