{"title":"Solinas素数上长整数模乘法的有效结构","authors":"Zheang Huai, K. Parhi, Xinmiao Zhang","doi":"10.1109/SiPS52927.2021.00034","DOIUrl":null,"url":null,"abstract":"Modular multiplication of very long integers is a key building block of fully homomorphic encryption and elliptic curve cryptography. The Karatsuba algorithm reduces the multiplication complexity by decomposing the operands into shorter segments. However, in the case of long numbers, adding up the segment products to derive the final product and then carrying out modular reduction as in previous designs can take many clock cycles. This paper focuses on moduli in the format of Solinas prime and proposes to integrate modular reduction into every segment product of the Karatsuba integer multiplication. As a result, the length of the intermediate results is further reduced and they can be added up simultaneously by using a carry-save adder at the cost of small area increase. Additionally, the computation scheduling are optimized to reduce the required number of registers and multiplexers. Complexity analysis shows that, for decomposition factors of 2, 3 and 4, our design requires on average 18.5% less clock cycles with only 5.9% area overhead and similar critical path compared to carrying out the modular reduction on the final product.","PeriodicalId":103894,"journal":{"name":"2021 IEEE Workshop on Signal Processing Systems (SiPS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Efficient Architecture for Long Integer Modular Multiplication over Solinas Prime\",\"authors\":\"Zheang Huai, K. Parhi, Xinmiao Zhang\",\"doi\":\"10.1109/SiPS52927.2021.00034\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Modular multiplication of very long integers is a key building block of fully homomorphic encryption and elliptic curve cryptography. The Karatsuba algorithm reduces the multiplication complexity by decomposing the operands into shorter segments. However, in the case of long numbers, adding up the segment products to derive the final product and then carrying out modular reduction as in previous designs can take many clock cycles. This paper focuses on moduli in the format of Solinas prime and proposes to integrate modular reduction into every segment product of the Karatsuba integer multiplication. As a result, the length of the intermediate results is further reduced and they can be added up simultaneously by using a carry-save adder at the cost of small area increase. Additionally, the computation scheduling are optimized to reduce the required number of registers and multiplexers. Complexity analysis shows that, for decomposition factors of 2, 3 and 4, our design requires on average 18.5% less clock cycles with only 5.9% area overhead and similar critical path compared to carrying out the modular reduction on the final product.\",\"PeriodicalId\":103894,\"journal\":{\"name\":\"2021 IEEE Workshop on Signal Processing Systems (SiPS)\",\"volume\":\"8 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 IEEE Workshop on Signal Processing Systems (SiPS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SiPS52927.2021.00034\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE Workshop on Signal Processing Systems (SiPS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SiPS52927.2021.00034","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Efficient Architecture for Long Integer Modular Multiplication over Solinas Prime
Modular multiplication of very long integers is a key building block of fully homomorphic encryption and elliptic curve cryptography. The Karatsuba algorithm reduces the multiplication complexity by decomposing the operands into shorter segments. However, in the case of long numbers, adding up the segment products to derive the final product and then carrying out modular reduction as in previous designs can take many clock cycles. This paper focuses on moduli in the format of Solinas prime and proposes to integrate modular reduction into every segment product of the Karatsuba integer multiplication. As a result, the length of the intermediate results is further reduced and they can be added up simultaneously by using a carry-save adder at the cost of small area increase. Additionally, the computation scheduling are optimized to reduce the required number of registers and multiplexers. Complexity analysis shows that, for decomposition factors of 2, 3 and 4, our design requires on average 18.5% less clock cycles with only 5.9% area overhead and similar critical path compared to carrying out the modular reduction on the final product.