Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'05)最新文献_第2页

Incorporating a secure coprocessor in the database-as-a-service model 在数据库即服务模型中加入安全协处理器

Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'05) Pub Date : 2005-01-17 DOI: 10.1109/IWIA.2005.28

Einar Mykletun, G. Tsudik

引用次数: 29

On the use of bit filters in shared nothing partitioned systems 位过滤器在无共享分区系统中的使用

Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'05) Pub Date : 2005-01-17 DOI: 10.1109/IWIA.2005.34

J. Aguilar-Saborit, V. Muntés-Mulero, C. Zuzarte, H. Pereyra, J. Larriba-Pey

{"title":"On the use of bit filters in shared nothing partitioned systems","authors":"J. Aguilar-Saborit, V. Muntés-Mulero, C. Zuzarte, H. Pereyra, J. Larriba-Pey","doi":"10.1109/IWIA.2005.34","DOIUrl":"https://doi.org/10.1109/IWIA.2005.34","url":null,"abstract":"Parallel query processing is in the core of many business analysis environments. Such applications impose a high demand on the computer hardware to achieve results in reasonable times, specially when queries are launched against huge amounts of warehouse data. We look into the problem of parallel query processing on large data sets focusing on a rational use of the network and memory resources. In this context, we propose a new protocol to make use of bit filters in parallel shared nothing systems for non-collocated joins. We call our protocol remote bit filters with requests (RBF/sub R/). We have implemented a prototype of RBF/sub R/ for the first time in a major commercial database, IBM/spl reg/ DB2 Universal Database/spl trade/(DB2 UDB). RBF/sub R/ has two important advantages over the previous usage of bit filters in the same context. First, it reduces the amount of memory used compared to previous solutions. This allows for the processing of more or larger queries. Second, the protocol itself has an insignificant impact on communication. This means that it is as efficient as the previous strategies, avoiding the saturation of the network in parallel intensive network usage environments.","PeriodicalId":103456,"journal":{"name":"Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'05)","volume":"161 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116637570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Understanding and comparing the performance of optimized JVMs 理解和比较优化后的jvm的性能

Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'05) Pub Date : 2005-01-17 DOI: 10.1109/IWIA.2005.44

D. Nicolaescu, A. Veidenbaum

{"title":"Understanding and comparing the performance of optimized JVMs","authors":"D. Nicolaescu, A. Veidenbaum","doi":"10.1109/IWIA.2005.44","DOIUrl":"https://doi.org/10.1109/IWIA.2005.44","url":null,"abstract":"Java virtual machines have different performance characteristics depending on their interpretation and just in time compilation strategies. These characteristics are even more complex when running on a modern out-of-order superscalar processor. This paper analyzes the behavior of the SPECjvm98 benchmarks on IBM's JikesRVM Java virtual machine executing on the IBM Power4 processor. Execution time parameters such as the number of instructions and cycles, the behavior of instruction and data caches, and the branching characteristics obtained from hardware performance counters are used to explain performance differences between interpreted, JIT compiled and dynamically optimized JVMs. Our goal is to understand benchmark and processor behavior with different JIT optimization options and strategies and to use this knowledge in design of future JVMs. The results show that the reduction in the number of executed instructions due to compiler optimizations is the main reason for improved performance. An increase in instruction level parallelism in compiled code provides further improvement. The increased ILP is in large part due to elimination of dependences in the optimized code.","PeriodicalId":103456,"journal":{"name":"Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'05)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122833903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Steering and forwarding techniques for reducing memory communication on a clustered microarchitecture 减少集群微架构上内存通信的转向和转发技术

Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'05) Pub Date : 2005-01-17 DOI: 10.1109/IWIA.2005.41

H. Irie, N. Hattori, M. Takada, N. Hatta, T. Toyoshima, S. Sakai

引用次数: 0

Optimal loop-unrolling mechanisms and architectural extensions for an energy-efficient design of shared register files in MPSoCs mpsoc中共享寄存器文件节能设计的最佳循环展开机制和体系结构扩展

Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'05) Pub Date : 2005-01-17 DOI: 10.1109/IWIA.2005.35

J. Ayala, David Atienza Alonso, M. López-Vallejo, J. Mendias, R. Hermida, C. López-Barrio

引用次数: 2

The bimode++ branch predictor 双模++分支预测器

Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'05) Pub Date : 2005-01-17 DOI: 10.1109/IWIA.2005.43

Kenji Kise, T. Katagiri, H. Honda, T. Yuba

{"title":"The bimode++ branch predictor","authors":"Kenji Kise, T. Katagiri, H. Honda, T. Yuba","doi":"10.1109/IWIA.2005.43","DOIUrl":"https://doi.org/10.1109/IWIA.2005.43","url":null,"abstract":"Modern wide-issue superscalar processors tend to adopt deeper pipelines in order to attain high clock rates. This trend increases the number of on-the-fly instructions in processors and a mispredicted branch can result in substantial amounts of wasted work. In order to mitigate these wasted works, an accurate branch prediction is required for the high performance processors. In order to improve the prediction accuracy, we propose the bimode++ branch predictor. It is an enhanced version of the bimode branch predictor. Throughout execution from the start to the end of a program, some branch instructions have the same result at all times. These branches are defined as extremely biased branches. The bimode++ branch predictor is unique in predicting the output of an extremely biased branch with a simple hardware structure. In addition, the bimode++ branch predictor improves the accuracy using the refined indexing and a fusion function. Our experimental results with benchmarks from SpecFP, SpecINT, multi-media and server area show that the bimode++ branch predictor can reduce the misprediction rate by 13.2% to the bimode and by 32.5% to the gshare.","PeriodicalId":103456,"journal":{"name":"Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'05)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133256555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13