{"title":"Design of the Hermes-RISC Processor","authors":"Mertoguno S.J., Bourbakis N.G.","doi":"10.1006/jmca.1995.0017","DOIUrl":"https://doi.org/10.1006/jmca.1995.0017","url":null,"abstract":"<div><p>This paper presents the structural design and the functional characteristics of a RISC processor called Hermes-RISC. The design of the Hermes-RISC processor is based on the study and evaluation of a variety of assembly instruction sets. The Hermes-RISC is a pipeline superscalar RISC processor with four superscalar units. The first stage evaluation of the Hermes-RISC performance is also presented here. This evaluation is based on the execution of a set of primitive processing tasks, such as summation, multiplication of numbers, multiplication of matrices, sorting, finding maximum values among a set of numbers, procedure calls, etc. Moreover, the performance of Hermes-RISC is compared with a variety of RISC processors.</p></div>","PeriodicalId":100806,"journal":{"name":"Journal of Microcomputer Applications","volume":"18 3","pages":"Pages 233-259"},"PeriodicalIF":0.0,"publicationDate":"1995-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1006/jmca.1995.0017","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71740258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An efficient architecture for a transputer based vehicle simulator","authors":"T. Srikanthan, K. Chan, S. K. Leong","doi":"10.1006/JMCA.1995.0015","DOIUrl":"https://doi.org/10.1006/JMCA.1995.0015","url":null,"abstract":"This paper presents an efficient architecture for the rendering and display sections of a vehicle simulator prototype. The architecture for the rendering stage, which consists of three independent concurrent units, has been optimised to support the two-layer dynamic load balancing technique. The display stage has also been partitioned to facilitate parallel updating of the pixel data to the dual frame buffers. The design of the frame buffers and the interface logic to access them by direct memory access (DMA) controllers (via three common address and data buses) and the colour video controller are also presented. Simulation results show that the adoption of DMA based memory transfer between the local memory of the transputer nodes and the frame buffers can alleviate the communication bottleneck prevalent in an earlier prototype.","PeriodicalId":100806,"journal":{"name":"Journal of Microcomputer Applications","volume":"73 4 1","pages":"203-213"},"PeriodicalIF":0.0,"publicationDate":"1995-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84722719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design of the Hermes-RISC processor","authors":"S. Mertoguno, N. Bourbakis","doi":"10.1006/JMCA.1995.0017","DOIUrl":"https://doi.org/10.1006/JMCA.1995.0017","url":null,"abstract":"This paper presents the structural design and the functional characteristics of a RISC processor called Hermes-RISC. The design of the Hermes-RISC processor is based on the study and evaluation of a variety of assembly instruction sets. The Hermes-RISC is a pipeline superscalar RISC processor with four superscalar units. The first stage evaluation of the Hermes-RISC performance is also presented here. This evaluation is based on the execution of a set of primitive processing tasks, such as summation, multiplication of numbers, multiplication of matrices, sorting, finding maximum values among a set of numbers, procedure calls, etc. Moreover, the performance of Hermes-RISC is compared with a variety of RISC processors.","PeriodicalId":100806,"journal":{"name":"Journal of Microcomputer Applications","volume":"88 1","pages":"233-259"},"PeriodicalIF":0.0,"publicationDate":"1995-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84857550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An efficient architecture for a transputer based vehicle simulator","authors":"Srikanthan T., Chan K.Y., Leong S.K.","doi":"10.1006/jmca.1995.0015","DOIUrl":"https://doi.org/10.1006/jmca.1995.0015","url":null,"abstract":"<div><p>This paper presents an efficient architecture for the rendering and display sections of a vehicle simulator prototype. The architecture for the rendering stage, which consists of three independent concurrent units, has been optimised to support the two-layer dynamic load balancing technique. The display stage has also been partitioned to facilitate parallel updating of the pixel data to the dual frame buffers. The design of the frame buffers and the interface logic to access them by direct memory access (DMA) controllers (via three common address and data buses) and the colour video controller are also presented. Simulation results show that the adoption of DMA based memory transfer between the local memory of the transputer nodes and the frame buffers can alleviate the communication bottleneck prevalent in an earlier prototype.</p></div>","PeriodicalId":100806,"journal":{"name":"Journal of Microcomputer Applications","volume":"18 3","pages":"Pages 203-213"},"PeriodicalIF":0.0,"publicationDate":"1995-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1006/jmca.1995.0015","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71740256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Parallel computation with dynamic load distribution for locally distributed Windows NT environments","authors":"Gerhard Eschelbeck","doi":"10.1006/jmca.1995.0014","DOIUrl":"https://doi.org/10.1006/jmca.1995.0014","url":null,"abstract":"<div><p>Today 's requirements for computational power are still not satisfied. One answer for this demand is expensive supercomputers. Another attempt is the collection of computational power in a network. Connected workstations operate for parallel computation. Our approach for collecting unused resources in workstation clusters enables dynamic distribution of computational load over the network. Any computer individually distinguishes the amount of server resources sharing for others in the network. Our architecture is based on the client /server model —clients divide potentially hard problems into sub problems and forward them to different servers in the network. The usage of standardized remote procedure calls (rpc) as the basic mechanism for transmission of data between the workstations allows the extension of the concept for heterogeneous environments. This article gives a discussion of our implementation for Windows NT and presents the latest benchmarks with two special parallel applications.</p></div>","PeriodicalId":100806,"journal":{"name":"Journal of Microcomputer Applications","volume":"18 3","pages":"Pages 193-201"},"PeriodicalIF":0.0,"publicationDate":"1995-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1006/jmca.1995.0014","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71740255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Application of microcomputer in submicron level measurements and control of a positioning device","authors":"N. Vira","doi":"10.1016/S0745-7138(05)80024-7","DOIUrl":"https://doi.org/10.1016/S0745-7138(05)80024-7","url":null,"abstract":"","PeriodicalId":100806,"journal":{"name":"Journal of Microcomputer Applications","volume":"2015 1","pages":"149-164"},"PeriodicalIF":0.0,"publicationDate":"1995-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82757905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Fuzzy logic-based variable structure controllers","authors":"Gamal M. Aly, Mohammed A. Tayeb","doi":"10.1016/S0745-7138(05)80022-3","DOIUrl":"https://doi.org/10.1016/S0745-7138(05)80022-3","url":null,"abstract":"<div><p>A fuzzy logic control scheme based on the variable structure system concept is presented. This scheme is introduced to eliminate the necessity of relying on the mathematical description of the system. The rule-based fuzzy model is developed in a linguistic description of the dynamic characteristics of the controlled process. Simulation results demonstrate the effectiveness of the proposed scheme as compared with the conventional variable structure systems.</p></div>","PeriodicalId":100806,"journal":{"name":"Journal of Microcomputer Applications","volume":"18 2","pages":"Pages 115-125"},"PeriodicalIF":0.0,"publicationDate":"1995-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/S0745-7138(05)80022-3","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71785315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A performance analysis of a microprogram-based coprocessor","authors":"A.A. Wardak, G.A. King, K. Walsh","doi":"10.1016/S0745-7138(05)80025-9","DOIUrl":"https://doi.org/10.1016/S0745-7138(05)80025-9","url":null,"abstract":"<div><p>A technique for evaluating the performance of an Am29300 microprogrammable computer board in comparison to a host (an MC68020 single-board computer) is presented. The Am29300 microprogrammable computer board in this application is used as a coprocessor to a general-purpose MC68020 single-board computer. The Am29300 microprogrammable coprocessor board is used for speeding up the highly-repetitive and time-consuming floating point processing functions involved in three-dimensional image generation. The performance analysis of the Am29300 micro-programmable coprocessor is evaluated in terms of MC68020 processor clock cycles. A mathematical expression, containing floating-point operations is chosen as an application example. The analysis in this application has shown that the Am29300 microprogrammable coprocessor is eight times faster than the MC68020, six times faster than the MC68030, and twice as fast as the MC86040 processor.</p></div>","PeriodicalId":100806,"journal":{"name":"Journal of Microcomputer Applications","volume":"18 2","pages":"Pages 165-181"},"PeriodicalIF":0.0,"publicationDate":"1995-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/S0745-7138(05)80025-9","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71785325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D.F. Lovely, T.W. Hruczkowski, B. Hudgins, K. Rush, J.R. Sexsmith, J. Rickards, E.N. Biden
{"title":"Intelligent ambulatory monitor for the collection of biomechanical data from within the workplace","authors":"D.F. Lovely, T.W. Hruczkowski, B. Hudgins, K. Rush, J.R. Sexsmith, J. Rickards, E.N. Biden","doi":"10.1016/S0745-7138(05)80023-5","DOIUrl":"https://doi.org/10.1016/S0745-7138(05)80023-5","url":null,"abstract":"<div><p>This paper describes the design and development of an eight-channel ambulatory monitor for use in ergonomic and rehabilitation studies. This portable, battery operated instrument is capable of recording various physiological and biomechanical parameters during the course of a working shift. By incorporating a digital signal processor within the instrument, sophisticated on-line processing is possible. The processed data is stored in a removable non-volatile memory module which can be interrogated by a PC type machine. Evaluation of the instrument in a laboratory setting has been performed to verify operation. In addition, clinical trials are presently underway in a hospital environment as part of an injury prevention program targeted towards nurses. It is proposed that this instrument can be used to determine compliance with such programs after the initial training phase and give some indication as to whether refresher courses are warranted.</p></div>","PeriodicalId":100806,"journal":{"name":"Journal of Microcomputer Applications","volume":"18 2","pages":"Pages 127-147"},"PeriodicalIF":0.0,"publicationDate":"1995-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/S0745-7138(05)80023-5","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71785316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A PC based CCD emulation system","authors":"Dinesh Kumar Gnanoba Rao, Goparaju Nagendra Rao, Yashwant Kumar Jain","doi":"10.1016/S0745-7138(05)80026-0","DOIUrl":"https://doi.org/10.1016/S0745-7138(05)80026-0","url":null,"abstract":"<div><p>A novel method of electrically emulating an area array charge coupled device (CCD) using a personal computer is described in this paper. A dual port memory is used to simulate the photosensitive area of the CCD. Suitable clocks are also generated as is done in the actual CCD system.</p><p>The CCD emulation system is useful for the development of any hardware and software which interfaces with a CCD. This system is used to test the on-board micro-processor used in the Indian Remote Sensing (IRS-1C) satellite.</p></div>","PeriodicalId":100806,"journal":{"name":"Journal of Microcomputer Applications","volume":"18 2","pages":"Pages 183-192"},"PeriodicalIF":0.0,"publicationDate":"1995-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/S0745-7138(05)80026-0","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71785317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}