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Proceedings. International Conference on Dependable Systems and Networks最新文献

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Secure INtrusion-Tolerant Replication on the Internet Internet上的安全容错复制
Proceedings. International Conference on Dependable Systems and Networks Pub Date : 2002-06-23 DOI: 10.1109/DSN.2002.1028897
C. Cachin, J. Poritz
{"title":"Secure INtrusion-Tolerant Replication on the Internet","authors":"C. Cachin, J. Poritz","doi":"10.1109/DSN.2002.1028897","DOIUrl":"https://doi.org/10.1109/DSN.2002.1028897","url":null,"abstract":"This paper describes a Secure INtrusion-Tolerant Replication Architecture (SINTRA) for coordination in asynchronous networks subject to Byzantine faults. SINTRA supplies a number of group communication primitives, such as binary and multi-valued Byzantine agreement, reliable and consistent broadcast, and an atomic broadcast channel. Atomic broadcast immediately provides secure state-machine replication. The protocols are designed for an asynchronous wide-area network, such as the Internet, where messages may be delayed indefinitely, the servers do not have access to a common clock, and up to one third of the servers may fail in potentially malicious ways. Security is achieved through the use of threshold public-key cryptography, in particular through a cryptographic common coin based on the Diffie-Hellman problem that underlies the randomized protocols in SINTRA. The implementation of SINTRA in Java is described and timing measurements are given for a test-bed of servers distributed over three continents. They show that extensive use of public-key cryptography does not impose a large overhead for secure coordination in wide-area networks.","PeriodicalId":93807,"journal":{"name":"Proceedings. International Conference on Dependable Systems and Networks","volume":"10 1","pages":"167-176"},"PeriodicalIF":0.0,"publicationDate":"2002-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78652559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 166
Analysis of failure and recovery rates in a wireless telecommunications system 无线通信系统的故障率和恢复率分析
Proceedings. International Conference on Dependable Systems and Networks Pub Date : 2002-06-23 DOI: 10.1109/DSN.2002.1029014
S. Matz, L. Votta, M. Malkawi
{"title":"Analysis of failure and recovery rates in a wireless telecommunications system","authors":"S. Matz, L. Votta, M. Malkawi","doi":"10.1109/DSN.2002.1029014","DOIUrl":"https://doi.org/10.1109/DSN.2002.1029014","url":null,"abstract":"We derive estimates of mean time to failure and mean time to recover/repair for both hardware and software in a large wireless telecommunications system, based on six months of manually recorded outage data. The observed failure and recovery distributions are not consistent with simple exponential processes. The data can be described by Weibull or two-stage hyper-exponential distributed processes. The duration distributions for scheduled and unscheduled software outages have very different characteristics. The complex distributions observed may be the composition of simple independent processes which cannot be separated in this data set due to a lack of adequately detailed information or proper characterization of outage causes. In this system we found a coverage of /spl sim/98% for autorecovery from unscheduled software failures with an autorepair fraction of /spl sim/36%.","PeriodicalId":93807,"journal":{"name":"Proceedings. International Conference on Dependable Systems and Networks","volume":"42 4 1","pages":"687-693"},"PeriodicalIF":0.0,"publicationDate":"2002-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79908458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 43
Transactional rollback for language-based systems 基于语言的系统的事务回滚
Proceedings. International Conference on Dependable Systems and Networks Pub Date : 2002-06-23 DOI: 10.1109/DSN.2002.1028929
A. Rudys, D. Wallach
{"title":"Transactional rollback for language-based systems","authors":"A. Rudys, D. Wallach","doi":"10.1109/DSN.2002.1028929","DOIUrl":"https://doi.org/10.1109/DSN.2002.1028929","url":null,"abstract":"Language run-time systems are routinely used to host potentially buggy or malicious codelets-software modules, agents, applets, etc.-in a secure environment. A number of techniques exist for managing access control to system services and even for terminating codelets once they have been determined to be misbehaving. However because codelets can be terminated anywhere in their execution, a codelet's internal state might become inconsistent; restarting the codelet could result in unexpected behavior. Any state the codelet shares with other codelets may likewise become inconsistent, destabilizing those codelets as well. To address these problems, we have designed a mechanism, strictly using code-to-code transformations, which provides transactional rollback support for codelets. Each instance of a codelet is run in its own transaction, and standard (ACID) transactional semantics apply. All changes made by the codelet are automatically rolled back when the corresponding transaction aborts. We discuss a transactional rollback implementation for Java, and present its performance.","PeriodicalId":93807,"journal":{"name":"Proceedings. International Conference on Dependable Systems and Networks","volume":"30 1","pages":"439-448"},"PeriodicalIF":0.0,"publicationDate":"2002-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88834806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Modeling the effect of technology trends on the soft error rate of combinational logic 技术发展趋势对组合逻辑软错误率的影响建模
Proceedings. International Conference on Dependable Systems and Networks Pub Date : 2002-06-23 DOI: 10.1109/DSN.2002.1028924
P. Shivakumar, M. Kistler, S. Keckler, D. Burger, L. Alvisi
{"title":"Modeling the effect of technology trends on the soft error rate of combinational logic","authors":"P. Shivakumar, M. Kistler, S. Keckler, D. Burger, L. Alvisi","doi":"10.1109/DSN.2002.1028924","DOIUrl":"https://doi.org/10.1109/DSN.2002.1028924","url":null,"abstract":"This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to-end model that enables us to compute the soft error rates (SER) for existing and future microprocessor-style designs. The model captures the effects of two important masking phenomena, electrical masking and latching-window masking, which inhibit soft errors in combinational logic. We quantify the SER due to high-energy neutrons in SRAM cells, latches, and logic circuits for feature sizes from 600 nm to 50 nm and clock periods from 16 to 6 fan-out-of-4 inverter delays. Our model predicts that the SER per chip of logic circuits will increase nine orders of magnitude from 1992 to 2011 and at that point will be comparable to the SER per chip of unprotected memory elements. Our result emphasizes that computer system designers must address the risks of soft errors in logic circuits for future designs.","PeriodicalId":93807,"journal":{"name":"Proceedings. International Conference on Dependable Systems and Networks","volume":"48 1","pages":"389-398"},"PeriodicalIF":0.0,"publicationDate":"2002-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89785049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1559
Caveat: a tool for software validation 警告:用于软件验证的工具
Proceedings. International Conference on Dependable Systems and Networks Pub Date : 2002-06-23 DOI: 10.1109/DSN.2002.1028953
P. Baudin, Anne Pacalet, J. Raguideau, D. Schoen, Nicky Williams
{"title":"Caveat: a tool for software validation","authors":"P. Baudin, Anne Pacalet, J. Raguideau, D. Schoen, Nicky Williams","doi":"10.1109/DSN.2002.1028953","DOIUrl":"https://doi.org/10.1109/DSN.2002.1028953","url":null,"abstract":"Caveat is a static analysis tool designed to help verify safety critical software. It operates on ANSI C programs. It was developed by CEA, the French nuclear agency and is used as an operational tool by Airbus-France and EdF, the French electricity company. It is mainly based on Hoare Logic and rewriting of first order logic predicates. The main features of Caveat are property synthesis, navigation facilities, and proof of properties.","PeriodicalId":93807,"journal":{"name":"Proceedings. International Conference on Dependable Systems and Networks","volume":"5 1","pages":"537-"},"PeriodicalIF":0.0,"publicationDate":"2002-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83413955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Performance analysis of a consensus algorithm combining stochastic activity networks and measurements 结合随机活动网络和测量的一致性算法的性能分析
Proceedings. International Conference on Dependable Systems and Networks Pub Date : 2002-06-23 DOI: 10.1109/DSN.2002.1028980
A. Coccoli, P. Urbán, A. Bondavalli
{"title":"Performance analysis of a consensus algorithm combining stochastic activity networks and measurements","authors":"A. Coccoli, P. Urbán, A. Bondavalli","doi":"10.1109/DSN.2002.1028980","DOIUrl":"https://doi.org/10.1109/DSN.2002.1028980","url":null,"abstract":"Protocols which solve agreement problems are essential building blocks for fault tolerant distributed applications. While many protocols have been published, little has been done to analyze their performance. This paper represents a starting point for such studies, by focusing on the consensus problem, a problem related to most other agreement problems. The paper analyzes the latency of a consensus algorithm designed for the asynchronous model with failure detectors, by combining experiments on a cluster of PCs and simulation using stochastic activity networks. We evaluated the latency in runs (1) with no failures nor failure suspicions, (2) with failures but no wrong suspicions and (3) with no failures but with (wrong) failure suspicions. We validated the adequacy and the usability of the stochastic activity network model by comparing experimental results with those obtained from the model. This has led us to identify limitations of the model and the measurements, and suggests new directions for evaluating the performance of agreement protocols.","PeriodicalId":93807,"journal":{"name":"Proceedings. International Conference on Dependable Systems and Networks","volume":"32 1","pages":"551-560"},"PeriodicalIF":0.0,"publicationDate":"2002-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82488669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
Libsafe: transparent system-wide protection against buffer overflow attacks Libsafe:透明的系统范围保护，防止缓冲区溢出攻击
Proceedings. International Conference on Dependable Systems and Networks Pub Date : 2002-06-23 DOI: 10.1109/DSN.2002.1028963
T. Tsai, Navjot Singh
{"title":"Libsafe: transparent system-wide protection against buffer overflow attacks","authors":"T. Tsai, Navjot Singh","doi":"10.1109/DSN.2002.1028963","DOIUrl":"https://doi.org/10.1109/DSN.2002.1028963","url":null,"abstract":"Libsafe is a practical solution that protects against the most common forms of buffer overflow attacks. Such attacks often result in granting the attacker full privileges on the target system. Libsafe is implemented as a shared library that intercepts calls to vulnerable standard library functions. Based on an inspection of the process stack and the function arguments, Libsafe ensures that no return addresses can be overwritten, thus preventing the most common form of buffer overflow attack.","PeriodicalId":93807,"journal":{"name":"Proceedings. International Conference on Dependable Systems and Networks","volume":"16 1","pages":"541-"},"PeriodicalIF":0.0,"publicationDate":"2002-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81945084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 41
Xception/sup TM/ - enhanced automated fault-injection environment xeption /sup TM/ -增强的自动故障注入环境
Proceedings. International Conference on Dependable Systems and Networks Pub Date : 2002-06-23 DOI: 10.1109/DSN.2002.1028978
R. Maia, L. Henriques, D. Costa, H. Madeira
{"title":"Xception/sup TM/ - enhanced automated fault-injection environment","authors":"R. Maia, L. Henriques, D. Costa, H. Madeira","doi":"10.1109/DSN.2002.1028978","DOIUrl":"https://doi.org/10.1109/DSN.2002.1028978","url":null,"abstract":"Discusses Xception, an automated fault injection environment that enables accurate and flexible V&V (verification & validation) and evaluation of mission and business critical computer systems using fault injection. Xception is designed to accommodate a variety of fault injection techniques (according to a wide range of configurations of the tool) and emulate in this way different classes of faults, with particular emphasis to hardware and software faults.","PeriodicalId":93807,"journal":{"name":"Proceedings. International Conference on Dependable Systems and Networks","volume":"88 1","pages":"547-"},"PeriodicalIF":0.0,"publicationDate":"2002-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88356400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Experimental evaluation of time-redundant execution for a brake-by-wire application 线控制动系统时间冗余执行的实验评价
Proceedings. International Conference on Dependable Systems and Networks Pub Date : 2002-06-23 DOI: 10.1109/DSN.2002.1028902
J. Aidemark, J. Vinter, P. Folkesson, J. Karlsson
{"title":"Experimental evaluation of time-redundant execution for a brake-by-wire application","authors":"J. Aidemark, J. Vinter, P. Folkesson, J. Karlsson","doi":"10.1109/DSN.2002.1028902","DOIUrl":"https://doi.org/10.1109/DSN.2002.1028902","url":null,"abstract":"This paper presents an experimental evaluation of a brake-by-wire application that tolerates transient faults by temporal error masking. A specially designed real-time kernel that masks errors by triple time-redundant execution and voting executes the application on a fail-stop computer node. The objective is to reduce the number of node failures by masking errors at the computer node level. The real-time kernel always executes the application twice to detect errors, and ensures that a fail-stop failure occurs if there is not enough CPU-time available for a third execution and voting. Fault injection experiments show that temporal error masking reduced the number of fail-stop failures by 42% compared to executing the brake-by-wire task without time redundancy.","PeriodicalId":93807,"journal":{"name":"Proceedings. International Conference on Dependable Systems and Networks","volume":"54 1","pages":"210-215"},"PeriodicalIF":0.0,"publicationDate":"2002-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88805594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
Jaca: a reflective fault injection tool based on patterns Jaca:基于模式的反射式故障注入工具
Proceedings. International Conference on Dependable Systems and Networks Pub Date : 2002-06-23 DOI: 10.1109/DSN.2002.1028934
E. Martins, C. M. F. Rubira, Nelson G. M. Leme
{"title":"Jaca: a reflective fault injection tool based on patterns","authors":"E. Martins, C. M. F. Rubira, Nelson G. M. Leme","doi":"10.1109/DSN.2002.1028934","DOIUrl":"https://doi.org/10.1109/DSN.2002.1028934","url":null,"abstract":"Jaca is a software fault injection tool that validates OO applications written in Java. Jaca's major goal is to inject faults using high-level programming features during runtime by corrupting attribute values, methods parameters or return values. Jaca's design was based on a set of patterns-the fault injection pattern system. This pattern describes a generic architecture defined from recurrent design aspects present in most fault injection tools. The objective was to reduce tool development time while enhancing qualities such as portability, extensibility, reusability, efficiency and robustness. The paper presents the pattern set and its use in Jaca's development. An extension of Jaca to consider injection at the assembly level is also presented to show how easy it is to add new features to the tool.","PeriodicalId":93807,"journal":{"name":"Proceedings. International Conference on Dependable Systems and Networks","volume":"3 1","pages":"483-487"},"PeriodicalIF":0.0,"publicationDate":"2002-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89698362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 72
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