2017 Conference on Design and Architectures for Signal and Image Processing (DASIP)最新文献_第2页

Proposition and evaluation of a real-time generic architecture for a laser stripe detection system on FPGA 基于FPGA的激光条纹检测系统实时通用架构的提出与评价

2017 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2017-09-01 DOI: 10.1109/DASIP.2017.8122110

Seher Colak, E. Dumas, V. Fresse, O. Alata

引用次数: 2

Detecting data-parallel synchronous dataflow graphs 检测数据并行同步数据流图

2017 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2017-09-01 DOI: 10.1109/DASIP.2017.8122118

Sudeep Kanur, J. Lilius, Johan Ersfolk

引用次数: 0

Hardware-software abandoned object detection vision system in heterogeneous zynq device 异构zynq设备中抛弃硬件软件的目标检测视觉系统

2017 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2017-09-01 DOI: 10.1109/DASIP.2017.8122122

T. Kryjak, Artur Skirzynski, M. Gorgon

引用次数: 0

The best of both: High-performance anc deterministic real-time executive by application-specific multi-core SoCs 两者兼而有之:通过特定于应用程序的多核soc实现高性能和确定性实时执行

2017 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2017-09-01 DOI: 10.1109/DASIP.2017.8122107

Steffen Vaas, Peter Ulbrich, M. Reichenbach, D. Fey

{"title":"The best of both: High-performance anc deterministic real-time executive by application-specific multi-core SoCs","authors":"Steffen Vaas, Peter Ulbrich, M. Reichenbach, D. Fey","doi":"10.1109/DASIP.2017.8122107","DOIUrl":"https://doi.org/10.1109/DASIP.2017.8122107","url":null,"abstract":"Embedded multi-core processors improve performance significantly and are desirable in many application-fields. This in particular includes safety-critical real-time systems, which typically require a deterministic temporal behavior. However, even tasks without dependencies running on different cores can interfere due to, sometimes hidden, shared hardware resources, such as common memories or buses. Consequently, only a pessimistic assumption of the worst-case execution time (WCET) that incorporates interference can be given. Hence, the aspired performance gain fizzles out in the poor temporal analyzability. Based on the fact that in safety-critical systems all tasks and their dependencies are known at compile-time, this paper presents an approach to generate application-specific, deterministic multi-core processor architectures for these systems. Thereby safety-critical tasks are executed on dedicated Deterministic Execution Units (DEUs) including lightweight, deterministic processor cores, bus systems, memories and peripherals. The remaining soft real-time tasks are executed on a general purpose multi-core processor that offers performance over determinism. Consequently, timing analysis for hard real-time tasks is significantly simplified, since interferences caused by shared resources and scheduling are effectively eliminated. To show the benefits of our approach, an application-specific architecture for a flight controller was generated and compared to an ARM Cortex-A9 dual-core as reference. Overall, we were able to significantly improve temporal properties of safety-critical tasks while preserving the overall performance for soft real-time tasks.","PeriodicalId":6637,"journal":{"name":"2017 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"7 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78960169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Single-FPGA complete 3D and 2D medical ultrasound imager 单fpga完整的三维和二维医学超声成像仪

2017 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2017-09-01 DOI: 10.1109/DASIP.2017.8122113

A. Ibrahim, W. Simon, Damien Doy, E. Pignat, F. Angiolini, M. Arditi, J. Thiran, G. Micheli

引用次数: 4

Embedded fluorescence lifetime determination for high throughput real-time droplet sorting with microfluidics 微流体高通量实时液滴分选的嵌入式荧光寿命测定

2017 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2017-09-01 DOI: 10.1109/DASIP.2017.8122129

T. Lieske, W. Uhring, N. Dumas, J. Léonard, D. Fey

{"title":"Embedded fluorescence lifetime determination for high throughput real-time droplet sorting with microfluidics","authors":"T. Lieske, W. Uhring, N. Dumas, J. Léonard, D. Fey","doi":"10.1109/DASIP.2017.8122129","DOIUrl":"https://doi.org/10.1109/DASIP.2017.8122129","url":null,"abstract":"Time-resolved fluorescence (TRF) analysis is considered to be among the primary research tools in biochemistry and biophysics. One application of this method is the investigation of biomolecular interactions with promising applications for biosensing. For the latter context, time-correlated single photon counting (TCSPC) is the most sensitive, hence preferred implementation of TRF. However, high throughput applications are presently limited by the maximum achievable photon acquisition rate, and even more by the data processing rate. The latter rate is actually limited by the computational complexity to estimate accurately the fluorescence lifetime from TCSPC data. Here we propose a solution that would enable the implementation of TRF detection for fluorescence-activated droplet sorting (FADS), a particularly high throughput, microfluidic-based technology. Most fluorescence lifetime algorithms require a large number of detected photons for an accurate lifetime computation. This paper presents an implementation based on a maximum likelihood estimator (MLE), enabling high precision estimation with a limited number of detected photons, significantly reducing the total measurement time. This speedup rapidly increases the input data rate. As a result, off-the-shelf embedded products cannot handle the data rates produced by current TCSPC units that are used to measure the fluorescence. Therefore, a configurable real-time capable hardware architecture is implemented on a field-programmable gate array (FPGA) that can handle the data rates of future TCSPC units, rendering high throughput droplet sorting with microfluidics possible.","PeriodicalId":6637,"journal":{"name":"2017 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"38 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75648080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Hardware-based architecture for asymmetric numeral systems entropy decoder 非对称数字系统熵解码器的硬件结构

2017 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2017-09-01 DOI: 10.1109/DASIP.2017.8122109

Seyyed Mahdi Najmabadi, Harsimran Singh Tungal, Trung-Hieu Tran, S. Simon

引用次数: 8

Power efficient dataflow design for a heterogeneous smart camera architecture 一种异构智能摄像头架构的高能效数据流设计

2017 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2017-09-01 DOI: 10.1109/DASIP.2017.8122128

Deepayan Bhowmik, Paulo Garcia, A. Wallace, Robert J. Stewart, G. Michaelson

{"title":"Power efficient dataflow design for a heterogeneous smart camera architecture","authors":"Deepayan Bhowmik, Paulo Garcia, A. Wallace, Robert J. Stewart, G. Michaelson","doi":"10.1109/DASIP.2017.8122128","DOIUrl":"https://doi.org/10.1109/DASIP.2017.8122128","url":null,"abstract":"Visual attention modelling characterises the scene to segment regions of visual interest and is increasingly being used as a pre-processing step in many computer vision applications including surveillance and security. Smart camera architectures are an emerging technology and a foundation of security and safety frameworks in modern vision systems. In this paper, we present a dataflow design of a visual saliency based camera architecture targeting a heterogeneous CPU+FPGA platform to propose a smart camera network infrastructure. The proposed design flow encompasses image processing algorithm implementation, hardware & software integration and network connectivity through a unified model. By leveraging the properties of the dataflow paradigm, we iteratively refine the algorithm specification into a deployable solution, addressing distinct requirements at each design stage: from algorithm accuracy to hardware-software interactions, real-time execution and power consumption. Our design achieved real-time run time performance and the power consumption of the optimised asynchronous design is reported at only 0.25 Watt. The resource usages on a Xilinx Zynq platform remains significantly low.","PeriodicalId":6637,"journal":{"name":"2017 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"79 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84108852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Enabling GPU software developers to optimize their applications — The LPGPU2 approach 使GPU软件开发人员能够优化他们的应用程序- lppu2方法

2017 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2017-09-01 DOI: 10.1109/DASIP.2017.8122116

B. Juurlink, J. Lucas, Nadjib Mammeri, G. Keramidas, Katerina Pontzolkova, I. Aransay, Chrysa Kokkala, Martyn Bliss, A. Richards

{"title":"Enabling GPU software developers to optimize their applications — The LPGPU2 approach","authors":"B. Juurlink, J. Lucas, Nadjib Mammeri, G. Keramidas, Katerina Pontzolkova, I. Aransay, Chrysa Kokkala, Martyn Bliss, A. Richards","doi":"10.1109/DASIP.2017.8122116","DOIUrl":"https://doi.org/10.1109/DASIP.2017.8122116","url":null,"abstract":"Low-power GPUs have become ubiquitous, they can be found in domains ranging from wearable and mobile computing to automotive systems. With this ubiquity has come a wider range of applications exploiting low-power GPUs, placing ever increasing demands on the expected performance and power efficiency of the devices. The LPGPU2 project is an EU-funded, Innovation Action, 30-month-project targeting to develop an analysis and visualization framework that enables GPU application developers to improve the performance and power consumption of their applications. To this end, the project follows a holistic approach. First, several applications (use cases) are being developed for or ported to low-power GPUs. These applications will be optimized using the tooling framework in the last phase of the project. In addition, power measurement devices and power models are devised that are 10× more accurate than the state of the art. The ultimate goal of the project is to promote open vendor-neutral standards via the Khronos group. This paper briefly reports on the achievements made in the first phase of the project (till month 18) and focuses on the progress made in applications; in power measurement, estimation, and modelling; and in the analysis and visualization tool suite.","PeriodicalId":6637,"journal":{"name":"2017 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"26 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82060300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Energy consumption characterization of a Massively Parallel Processor Array (MPPA) platform running a hyperspectral SVM classifier 运行高光谱支持向量机分类器的大规模并行处理器阵列(MPPA)平台的能耗表征

2017 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2017-09-01 DOI: 10.1109/DASIP.2017.8122112

D. Madroñal, R. Lazcano, H. Fabelo, S. Ortega, R. Salvador, G. Callicó, E. Juárez, C. Sanz

{"title":"Energy consumption characterization of a Massively Parallel Processor Array (MPPA) platform running a hyperspectral SVM classifier","authors":"D. Madroñal, R. Lazcano, H. Fabelo, S. Ortega, R. Salvador, G. Callicó, E. Juárez, C. Sanz","doi":"10.1109/DASIP.2017.8122112","DOIUrl":"https://doi.org/10.1109/DASIP.2017.8122112","url":null,"abstract":"In this paper, a Massively Parallel Processor Array platform is characterized in terms of energy consumption using a Support Vector Machine for hyperspectral image classification. This platform gathers 16 clusters composed of 16 cores each, i.e., 256 processors working in parallel. The objective of the work is to associate power dissipation and energy consumed by the platform with the different resources of the architecture. Experimenting with a hyperspectral SVM classifier, this study has been conducted using three strategies: i) modifying the number of processing elements, i.e., clusters and cores, ii) increasing system frequency, and iii) varying the number of active communication links during the analysis, i.e., I/Os and DMAs. As a result, a relationship between the energy consumption and the active platform resources has been exposed using two different parallelization strategies. Finally, the implementation that fully exploits the parallelization possibilities working at 500MHz has been proven to be also the most efficient one, as it reduces the energy consumption by 98% when compared to the sequential version running at 400MHz.","PeriodicalId":6637,"journal":{"name":"2017 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"8 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82068279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6