2015 IEEE 22nd Symposium on Computer Arithmetic最新文献_第4页

Pain versus Gain in the Hardware Design of FPUs and Supercomputers fpu和超级计算机硬件设计中的痛苦与收获

2015 IEEE 22nd Symposium on Computer Arithmetic Pub Date : 2005-06-27 DOI: 10.1109/ARITH.2005.33

Roger A. Golliver, S. M. Müller, S. Oberman, M. Schmookler, Debjit Das Sarma, A. Beaumont-Smith

{"title":"Pain versus Gain in the Hardware Design of FPUs and Supercomputers","authors":"Roger A. Golliver, S. M. Müller, S. Oberman, M. Schmookler, Debjit Das Sarma, A. Beaumont-Smith","doi":"10.1109/ARITH.2005.33","DOIUrl":"https://doi.org/10.1109/ARITH.2005.33","url":null,"abstract":"In 1990 there was a dramatic change in the overall design of floating-point units (FPUs) with the introduction of the fused multiply-add dataflow. This design is common today due to its performance advantage over separated units. Recently the constraining parameters have been changing for sub 10 micron technologies and the resulting designs are focusing on increasing the frequency at the cost of pipeline depth. Wire lengths are a crucial design parameter and there is a great deal of effort spent in floorplanning the execution elements to be very close together. It is now typical that a signal sent across an FPU may take 1 or more clock cycles. Thus, the physical design is very important and requires global optimizations of placement of macros as well as complex power reduction. Additionally technology scaling continues to decrease feature sizes and more execution units or even processor cores can be placed on a chip. Execution units such as Decimal FPUs are in product plans. There are single chip designs with 8 vector processing units which are used to accelerate the video games we play. The processing power in these single chip game processors is the equivalent of supercomputers. What is the next trendsetting design or key problem in computer arithmetic? We have asked a panel of expert arithmetic unit hardware designers to discuss the current pain versus gain tradeoffs and to speculate on the future of arithmetic design. Panelists:","PeriodicalId":6526,"journal":{"name":"2015 IEEE 22nd Symposium on Computer Arithmetic","volume":"119 1","pages":"39"},"PeriodicalIF":0.0,"publicationDate":"2005-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80393076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Computer Arithmetic-A Processor Architect's Perspective 计算机算术——处理器架构师的视角

2015 IEEE 22nd Symposium on Computer Arithmetic Pub Date : 2001-06-11 DOI: 10.1109/ARITH.2001.10003

R. Lee

引用次数: 4

Computer Arithmetic - A Programmer's Perspective 计算机算术——一个程序员的视角

2015 IEEE 22nd Symposium on Computer Arithmetic Pub Date : 1999-04-14 DOI: 10.1109/ARITH.1999.10005

R. Brent

引用次数: 1

Fast hardware units for the computation of accurate dot products 用于精确点积计算的快速硬件单元

2015 IEEE 22nd Symposium on Computer Arithmetic Pub Date : 1991-01-01 DOI: 10.1109/ARITH.1991.145536

A. Knöfel

引用次数: 3

Systolic arrays for integer Chinese remaindering 用于整型中文余数的收缩数组

2015 IEEE 22nd Symposium on Computer Arithmetic Pub Date : 1989-09-06 DOI: 10.1109/ARITH.1989.72829

Ç. Koç, P. Cappello

引用次数: 5

A family of CMOS floating point arithmetic chips 一种CMOS浮点运算芯片

2015 IEEE 22nd Symposium on Computer Arithmetic Pub Date : 1985-06-04 DOI: 10.1109/ARITH.1985.6158945

J. Eldon

引用次数: 1

Foundations of finite precision arithmetic 有限精度算术的基础

2015 IEEE 22nd Symposium on Computer Arithmetic Pub Date : 1972-05-15 DOI: 10.1109/ARITH.1972.6153887

D. Matula

引用次数: 4

Analog techniques for residue operations 残余操作的模拟技术

2015 IEEE 22nd Symposium on Computer Arithmetic Pub Date : 1972-05-15 DOI: 10.1109/ARITH.1972.6153892

T. L. Cauthen, T. Rao

{"title":"Analog techniques for residue operations","authors":"T. L. Cauthen, T. Rao","doi":"10.1109/ARITH.1972.6153892","DOIUrl":"https://doi.org/10.1109/ARITH.1972.6153892","url":null,"abstract":"The precision required for residue operations is primarily associated with resistive components and operational amplifiers. However, technology has advanced to the point that analog components can be built to an accuracy of less than one tenth of one percent (at least with discrete components). Companies are attempting to build DAC'S with fifteen (15) bit accuracy which will settle to the least significant bit in one hundred (100) nanoseconds. None are commercially available but seven or eight bit DAC's with settling times on the order of one hundred (100) nanoseconds are not uncommon. Sixteen (16) bit ADC's have been announced recently as a result of new analog components. It is not uncommon to find operational amplifiers on the market with gain bandwidth products in excess of one hundred fifty (150) megahertz and linearities on the order of one tenth of one percent. One can also find analog voltage comparators (such as the Motorola MC1650) which has a hysteresis of ten millivolts and a switching speed of less than two nanoseconds. Shotkey diodes have been introduced which allow transistors to switch in less than one and one-half nanoseconds, and manufacturers have learned to build both active and passive components to a tolerance of less than one-tenth of one percent.","PeriodicalId":6526,"journal":{"name":"2015 IEEE 22nd Symposium on Computer Arithmetic","volume":"1 1","pages":"1-23"},"PeriodicalIF":0.0,"publicationDate":"1972-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88001938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Multiresidue codes for double error correction 双重纠错的多残码

2015 IEEE 22nd Symposium on Computer Arithmetic Pub Date : 1972-05-15 DOI: 10.1109/ARITH.1972.6153889

P. Monteiro, T. Rao

引用次数: 2

A simulative study of correlated error propagation in various finite arithmetics 各种有限算法中相关误差传播的仿真研究

2015 IEEE 22nd Symposium on Computer Arithmetic Pub Date : 1972-05-15 DOI: 10.1109/ARITH.1972.6153915

J. Marasa, D. Matula

引用次数: 1