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2016 Formal Methods in Computer-Aided Design (FMCAD)最新文献

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Bounded Verification of Past LTL 过去LTL的有界验证
2016 Formal Methods in Computer-Aided Design (FMCAD) Pub Date : 2004-11-15 DOI: 10.1007/978-3-540-30494-4_18
A. Cimatti, Marco Roveri, Daniel Sheridan
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引用次数: 41
A Partitioning Methodology for BDD-Based Verification 基于bdd验证的分区方法
2016 Formal Methods in Computer-Aided Design (FMCAD) Pub Date : 2004-11-15 DOI: 10.1007/978-3-540-30494-4_28
D. Sahoo, S. Iyer, J. Jain, Christian Stangier, A. Narayan, D. Dill, E. Emerson
{"title":"A Partitioning Methodology for BDD-Based Verification","authors":"D. Sahoo, S. Iyer, J. Jain, Christian Stangier, A. Narayan, D. Dill, E. Emerson","doi":"10.1007/978-3-540-30494-4_28","DOIUrl":"https://doi.org/10.1007/978-3-540-30494-4_28","url":null,"abstract":"","PeriodicalId":6479,"journal":{"name":"2016 Formal Methods in Computer-Aided Design (FMCAD)","volume":"3 1","pages":"399-413"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80258824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
A Simple Method for Parameterized Verification of Cache Coherence Protocols 缓存一致性协议参数化验证的一种简单方法
2016 Formal Methods in Computer-Aided Design (FMCAD) Pub Date : 2004-11-15 DOI: 10.1007/978-3-540-30494-4_27
Ching-Tsun Chou, P. K. Mannava, Seungjoon Park
{"title":"A Simple Method for Parameterized Verification of Cache Coherence Protocols","authors":"Ching-Tsun Chou, P. K. Mannava, Seungjoon Park","doi":"10.1007/978-3-540-30494-4_27","DOIUrl":"https://doi.org/10.1007/978-3-540-30494-4_27","url":null,"abstract":"","PeriodicalId":6479,"journal":{"name":"2016 Formal Methods in Computer-Aided Design (FMCAD)","volume":"34 1","pages":"382-398"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89710818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 106
Bounded Probabilistic Model Checking with the Muralpha Verifier 用Muralpha验证器进行有界概率模型检验
2016 Formal Methods in Computer-Aided Design (FMCAD) Pub Date : 2004-11-15 DOI: 10.1007/978-3-540-30494-4_16
G. D. Penna, B. Intrigila, I. Melatti, E. Tronci, M. V. Zilli
{"title":"Bounded Probabilistic Model Checking with the Muralpha Verifier","authors":"G. D. Penna, B. Intrigila, I. Melatti, E. Tronci, M. V. Zilli","doi":"10.1007/978-3-540-30494-4_16","DOIUrl":"https://doi.org/10.1007/978-3-540-30494-4_16","url":null,"abstract":"","PeriodicalId":6479,"journal":{"name":"2016 Formal Methods in Computer-Aided Design (FMCAD)","volume":"40 1","pages":"214-229"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75005077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
A Methodology for the Formal Verification of FFT Algorithms in HOL holl中FFT算法的形式化验证方法
2016 Formal Methods in Computer-Aided Design (FMCAD) Pub Date : 2004-11-15 DOI: 10.1007/978-3-540-30494-4_4
Behzad Akbarpour, S. Tahar
{"title":"A Methodology for the Formal Verification of FFT Algorithms in HOL","authors":"Behzad Akbarpour, S. Tahar","doi":"10.1007/978-3-540-30494-4_4","DOIUrl":"https://doi.org/10.1007/978-3-540-30494-4_4","url":null,"abstract":"","PeriodicalId":6479,"journal":{"name":"2016 Formal Methods in Computer-Aided Design (FMCAD)","volume":"1 1","pages":"37-51"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82447940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Extending Extended Vacuity 可拓扩展真空
2016 Formal Methods in Computer-Aided Design (FMCAD) Pub Date : 2004-11-15 DOI: 10.1007/978-3-540-30494-4_22
A. Gurfinkel, M. Chechik
{"title":"Extending Extended Vacuity","authors":"A. Gurfinkel, M. Chechik","doi":"10.1007/978-3-540-30494-4_22","DOIUrl":"https://doi.org/10.1007/978-3-540-30494-4_22","url":null,"abstract":"","PeriodicalId":6479,"journal":{"name":"2016 Formal Methods in Computer-Aided Design (FMCAD)","volume":"26 1","pages":"306-321"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75975177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
Non-miter-based Combinational Equivalence Checking by Comparing BDDs with Different Variable Orders 比较不同变量阶bdd的非正交组合等价性检验
2016 Formal Methods in Computer-Aided Design (FMCAD) Pub Date : 2004-11-15 DOI: 10.1007/978-3-540-30494-4_11
In-Ho Moon, C. Pixley
{"title":"Non-miter-based Combinational Equivalence Checking by Comparing BDDs with Different Variable Orders","authors":"In-Ho Moon, C. Pixley","doi":"10.1007/978-3-540-30494-4_11","DOIUrl":"https://doi.org/10.1007/978-3-540-30494-4_11","url":null,"abstract":"","PeriodicalId":6479,"journal":{"name":"2016 Formal Methods in Computer-Aided Design (FMCAD)","volume":"233 1","pages":"144-158"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75990865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Memory Efficient All-Solutions SAT Solver and Its Application for Reachability Analysis 存储器高效全解SAT求解器及其在可达性分析中的应用
2016 Formal Methods in Computer-Aided Design (FMCAD) Pub Date : 2004-11-15 DOI: 10.1007/978-3-540-30494-4_20
O. Grumberg, A. Schuster, Avi Yadgar
{"title":"Memory Efficient All-Solutions SAT Solver and Its Application for Reachability Analysis","authors":"O. Grumberg, A. Schuster, Avi Yadgar","doi":"10.1007/978-3-540-30494-4_20","DOIUrl":"https://doi.org/10.1007/978-3-540-30494-4_20","url":null,"abstract":"","PeriodicalId":6479,"journal":{"name":"2016 Formal Methods in Computer-Aided Design (FMCAD)","volume":"39 1","pages":"275-289"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72974561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 66
Verification of Analog and Mixed-Signal Circuits Using Hybrid System Techniques 用混合系统技术验证模拟和混合信号电路
2016 Formal Methods in Computer-Aided Design (FMCAD) Pub Date : 2004-11-15 DOI: 10.1007/978-3-540-30494-4_3
T. Dang, Alexandre Donzé, O. Maler
{"title":"Verification of Analog and Mixed-Signal Circuits Using Hybrid System Techniques","authors":"T. Dang, Alexandre Donzé, O. Maler","doi":"10.1007/978-3-540-30494-4_3","DOIUrl":"https://doi.org/10.1007/978-3-540-30494-4_3","url":null,"abstract":"","PeriodicalId":6479,"journal":{"name":"2016 Formal Methods in Computer-Aided Design (FMCAD)","volume":"141 1","pages":"21-36"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78898822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 137
Integrating Reasoning About Ordinal Arithmetic into ACL2 将序数推理集成到ACL2中
2016 Formal Methods in Computer-Aided Design (FMCAD) Pub Date : 2004-11-15 DOI: 10.1007/978-3-540-30494-4_7
P. Manolios, D. Vroon
{"title":"Integrating Reasoning About Ordinal Arithmetic into ACL2","authors":"P. Manolios, D. Vroon","doi":"10.1007/978-3-540-30494-4_7","DOIUrl":"https://doi.org/10.1007/978-3-540-30494-4_7","url":null,"abstract":"","PeriodicalId":6479,"journal":{"name":"2016 Formal Methods in Computer-Aided Design (FMCAD)","volume":"17 1","pages":"82-97"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87825256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
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