Design Automation for Embedded Systems最新文献_第3页

Emulation and verification framework for MPSoC based on NoC and RISC-V 基于NoC和RISC-V的MPSoC仿真与验证框架

IF 1.4 4区计算机科学

Design Automation for Embedded Systems Pub Date : 2022-09-14 DOI: 10.1007/s10617-022-09265-1

Mostafa Khamis, Sameh El-Ashry, Mohamed Abdelsalam, M. El-Kharashi, A. Shalaby

引用次数: 3

Optimization based on the minimum maximal k-partial-matching problem of finite states machines with input multiplexing 输入复用有限状态机的最小极大k部分匹配优化

IF 1.4 4区计算机科学

Design Automation for Embedded Systems Pub Date : 2022-06-01 DOI: 10.1007/s10617-022-09259-z

I. Garcia-Vargas, Raouf Senhadji-Navarro

引用次数: 1

Selective register-file cache: an energy saving technique for embedded processor architecture 选择性寄存器文件缓存:一种嵌入式处理器架构的节能技术

IF 1.4 4区计算机科学

Design Automation for Embedded Systems Pub Date : 2022-05-29 DOI: 10.1007/s10617-022-09264-2

Sumanth Gudaparthi, R. Shrestha

引用次数: 1

Retraction Note to: Test data compression for digital circuits using tetrad state skip scheme 撤回说明：使用四态跳过方案测试数字电路的数据压缩

IF 1.4 4区计算机科学

Design Automation for Embedded Systems Pub Date : 2022-05-09 DOI: 10.1007/s10617-022-09261-5

Lokesh Sivanandam, Uma Maheswari Oorkavalan, S. Periyasamy

引用次数: 1

Retraction Note to: A novel Gini index decision tree data mining method with neural network classifiers for prediction of heart disease 一种新的基于神经网络分类器的基尼指数决策树数据挖掘方法用于心脏病预测

IF 1.4 4区计算机科学

Design Automation for Embedded Systems Pub Date : 2022-05-09 DOI: 10.1007/s10617-022-09260-6

K. Mathan, P. Kumar, Parthasarathy Panchatcharam, Gunasekaran Manogaran, R. Varadharajan

引用次数: 0

Retraction Note to: QOS distributed routing protocol for mobile ad-hoc wireless networks using intelligent packet carrying systems 使用智能分组承载系统的移动自组织无线网络的QOS分布式路由协议

IF 1.4 4区计算机科学

Design Automation for Embedded Systems Pub Date : 2022-05-09 DOI: 10.1007/s10617-022-09262-4

T. Murugeswari, S. Rathi

引用次数: 0

Efficient placement and migration policies for an STT-RAM based hybrid L1 cache for intermittently powered systems 用于间歇供电系统的基于STT-RAM的混合L1缓存的高效放置和迁移策略

IF 1.4 4区计算机科学

Design Automation for Embedded Systems Pub Date : 2022-03-04 DOI: 10.1007/s10617-023-09272-w

S. Badri, Mukesh Saini, N. Goel

引用次数: 2

Auto implementation of parallel hardware architecture for Aho-Corasick algorithm Aho-Corasick算法并行硬件架构的自动实现

IF 1.4 4区计算机科学

Design Automation for Embedded Systems Pub Date : 2022-01-23 DOI: 10.1007/s10617-021-09257-7

M. Najam-ul-Islam, F. Zahra, A. Jafri, Roman Shah, Masood Ul Hassan, Muhammad Rashid

引用次数: 1

An energy efficient multi-target binary translator for instruction and data level parallelism exploitation 一个节能的多目标二进制翻译指令和数据级并行开发

IF 1.4 4区计算机科学

Design Automation for Embedded Systems Pub Date : 2022-01-14 DOI: 10.1007/s10617-021-09258-6

Tiago Knorst, Julio Vicenzi, Michael G. Jordan, Jonathan H. de Almeida, Guilherme Korol, Antonio C. S. Beck, Mateus B. Rutzig

{"title":"An energy efficient multi-target binary translator for instruction and data level parallelism exploitation","authors":"Tiago Knorst, Julio Vicenzi, Michael G. Jordan, Jonathan H. de Almeida, Guilherme Korol, Antonio C. S. Beck, Mateus B. Rutzig","doi":"10.1007/s10617-021-09258-6","DOIUrl":"https://doi.org/10.1007/s10617-021-09258-6","url":null,"abstract":"<p>Embedded devices are omnipresent in our daily routine, from smartphones to home appliances, that run data and control-oriented applications. To maximize the energy-performance tradeoff, data and instruction-level parallelism are exploited by using superscalar and specific accelerators. However, as such devices have severe time-to-market, binary compatibility should be maintained to avoid recurrent engineering, which is not considered in current embedded processors. This work visited a set of embedded applications showing the need for concurrent ILP and DLP exploitation. For that, we propose a Hybrid Multi-Target Binary Translator (HMTBT) to transparently exploit ILP and DLP by using a CGRA and ARM NEON engine as targeted accelerators. Results show that HMTBT transparently achieves 24% performance improvements and 54% energy savings over an OoO superscalar processor coupled to an ARM NEON engine. The proposed approach improves performance and energy in 10%, 24% over decoupled binary translators using the same accelerator with the same ILP and DLP capabilities.</p>","PeriodicalId":50594,"journal":{"name":"Design Automation for Embedded Systems","volume":"06 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2022-01-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138524225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

New paradigm of FPGA-based computational intelligence from surveying the implementation of DNN accelerators 基于fpga的计算智能新范式——深度神经网络加速器的实现

IF 1.4 4区计算机科学

Design Automation for Embedded Systems Pub Date : 2022-01-12 DOI: 10.1007/s10617-021-09256-8

Yang You, Yinghui Chang, Weikang Wu, Bingrui Guo, Hongyin Luo, Xiaojie Liu, Bijing Liu, Kairong Zhao, Shan He, Lin Li, Donghui Guo

{"title":"New paradigm of FPGA-based computational intelligence from surveying the implementation of DNN accelerators","authors":"Yang You, Yinghui Chang, Weikang Wu, Bingrui Guo, Hongyin Luo, Xiaojie Liu, Bijing Liu, Kairong Zhao, Shan He, Lin Li, Donghui Guo","doi":"10.1007/s10617-021-09256-8","DOIUrl":"https://doi.org/10.1007/s10617-021-09256-8","url":null,"abstract":"<p>With the rapid development of Artificial Intelligence, Internet of Things, 5G, and other technologies, a number of emerging intelligent applications represented by image recognition, voice recognition, autonomous driving, and intelligent manufacturing have appeared. These applications require efficient and intelligent processing systems for massive data calculations, so it is urgent to apply better DNN in a faster way. Although, compared with GPU, FPGA has a higher energy efficiency ratio, and shorter development cycle and better flexibility than ASIC. However, FPGA is not a perfect hardware platform either for computational intelligence. This paper provides a survey of the latest acceleration work related to the familiar DNNs and proposes three new directions to break the bottleneck of the DNN implementation. So as to improve calculating speed and energy efficiency of edge devices, intelligent embedded approaches including model compression and optimized data movement of the entire system are most commonly used. With the gradual slowdown of Moore’s Law, the traditional Von Neumann Architecture generates a “Memory Wall” problem, resulting in more power-consuming. In-memory computation will be the right medicine in the post-Moore law era. More complete software/hardware co-design environment will direct researchers’ attention to explore deep learning algorithms and run the algorithm on the hardware level in a faster way. These new directions start a relatively new paradigm in computational intelligence, which have attracted substantial attention from the research community and demonstrated greater potential over traditional techniques.</p>","PeriodicalId":50594,"journal":{"name":"Design Automation for Embedded Systems","volume":"15 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2022-01-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138524218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0