{"title":"The Need for Intrinsic Hardware Security Below 65nm","authors":"Mathias Wagner","doi":"10.1109/FDTC.2015.21","DOIUrl":"https://doi.org/10.1109/FDTC.2015.21","url":null,"abstract":"With the continuing progress in semiconductor technology the design and certification of security microcontrollers faces new challenges. This presentation looks at the impact of technologies below 65nm from a manufacturer's perspective, analysing the changes in effectiveness and necessary effort of different attack techniques, and presenting scenarios that showcase the need for hardware security while balancing performance, engineering effort and production cost.","PeriodicalId":444709,"journal":{"name":"2015 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121992017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Improving Fault Attacks on Embedded Software Using RISC Pipeline Characterization","authors":"Bilgiday Yuce, N. F. Ghalaty, P. Schaumont","doi":"10.1109/FDTC.2015.16","DOIUrl":"https://doi.org/10.1109/FDTC.2015.16","url":null,"abstract":"A fault attack becomes more efficient when the fault behavior, the response of a device to a fault injection, is precisely understood. In this paper, we present a methodology for fault attacks and their analysis on pipelined RISC processors. For complex hardware structures such as microprocessor pipelines, modeling the fault behavior can become challenging. By analyzing the structure of the RISC pipeline, we obtain insight into the most likely faults, and we are able to pinpoint the most sensitive points during execution of a cryptographic software program. We use this result to apply a recent class of fault injection attacks, so-called biased fault injection attacks, to two different software implementations of AES. Our target microprocessor is a 7-stage pipeline LEON3, mapped into a Spartan6 FPGA. The paper explains the methodology, the fault injection setup, and the fault analysis on the embedded software design of AES. Our results are useful for embedded software designers who have a need to understand the fault attack sensitivity of their implementation, as well as for security engineers who are in charge of improving countermeasures, in hardware or in software, against fault attacks.","PeriodicalId":444709,"journal":{"name":"2015 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123838541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}