2003 IEEE International Workshop on Computer Architectures for Machine Perception最新文献

Monitoring terrain database integrity through aircraft sensor consistency checking: architecture and flight test results 通过飞机传感器一致性检查监测地形数据库完整性:架构和飞行测试结果

2003 IEEE International Workshop on Computer Architectures for Machine Perception Pub Date : 2003-05-12 DOI: 10.1109/CAMP.2003.1598153

M. U. de Haag, J. Sayre, J. Campbell, S. Young

引用次数: 0

Memory considerations for high performance SIMD systems with on-chip control 具有片上控制的高性能SIMD系统的内存考虑

2003 IEEE International Workshop on Computer Architectures for Machine Perception Pub Date : 2003-05-12 DOI: 10.1109/CAMP.2003.1598157

M. Herbordt, Jade Cravyt, Calvin Lint

引用次数: 0

A parallel algorithm and architecture for object recognition in images 图像中目标识别的并行算法和体系结构

2003 IEEE International Workshop on Computer Architectures for Machine Perception Pub Date : 2003-05-12 DOI: 10.1109/CAMP.2003.1598158

K. Sitaraman, A. Ejnioui, N. Ranganathan

{"title":"A parallel algorithm and architecture for object recognition in images","authors":"K. Sitaraman, A. Ejnioui, N. Ranganathan","doi":"10.1109/CAMP.2003.1598158","DOIUrl":"https://doi.org/10.1109/CAMP.2003.1598158","url":null,"abstract":"The problem of tree pattern matching for object recognition in images is computationally intensive in nature. In two-dimensional images, the objects can be represented through multiscale decomposition as tree structures. The pattern tree representing an object can be matched with a subject tree representing an image in order to detect the objects within the image. Several sequential, parallel and hardware algorithms exist in the literature for tree pattern matching. In this paper, we describe a new parallel algorithm and its realization as a VLSI chip for tree pattern matching. The hardware algorithm is based on a linear array of processing elements (PEs) where the pattern matching is done in a pipelined fashion relying on nearest-neighbor communication between the PE's and the subject and pattern trees of arbitrary length can be processed using a fixed size PE array. The algorithm has an improved execution time of O(lceilm/arceiln) required to perform the matching where m, a and n are the sizes of the pattern tree, processor array, subject tree respectively. A prototype CMOS VLSI chip implementing the proposed algorithm has been designed and verified. It is shown that the hardware algorithm proposed in this work represent a sign improvement in terms of computational complexity, data flow, and architecture over the ones previously proposed for this problem","PeriodicalId":443821,"journal":{"name":"2003 IEEE International Workshop on Computer Architectures for Machine Perception","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114637575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A comparison of hardware resources required by real-time stereo dense algorithms 实时立体密集算法所需硬件资源的比较

2003 IEEE International Workshop on Computer Architectures for Machine Perception Pub Date : 2003-05-12 DOI: 10.1109/CAMP.2003.1598176

M. Perez, F. Cabestaing

引用次数: 5

System on chip evolution of a SIMD architecture for image processing 用于图像处理的SIMD体系结构的片上系统演变

2003 IEEE International Workshop on Computer Architectures for Machine Perception Pub Date : 2003-05-12 DOI: 10.1109/CAMP.2003.1598175

J. Denoulet, A. Mérigot

引用次数: 5

Design of a language-independent parallel string matching unit for NLP 面向自然语言处理的并行字符串匹配单元设计

2003 IEEE International Workshop on Computer Architectures for Machine Perception Pub Date : 2003-05-12 DOI: 10.1109/CAMP.2003.1598159

V. S. Murty, P. C. Reghu Raj, S. Raman

引用次数: 2

A multiscale technique for optical flow computation using piecewise affine approximation 基于分段仿射近似的多尺度光流计算技术

2003 IEEE International Workshop on Computer Architectures for Machine Perception Pub Date : 2003-05-12 DOI: 10.1109/CAMP.2003.1598167

H. Le, G. Seetharaman, B. Zavidovique

引用次数: 2

Design and implementation of a high performance matrix multiplier core for Xilinx Virtex FPGAs Xilinx Virtex fpga高性能矩阵乘法器核心的设计与实现

2003 IEEE International Workshop on Computer Architectures for Machine Perception Pub Date : 2003-05-12 DOI: 10.1109/CAMP.2003.1598160

S. Belkacemi, K. Benkrid, D. Crookes, A. Benkrid

{"title":"Design and implementation of a high performance matrix multiplier core for Xilinx Virtex FPGAs","authors":"S. Belkacemi, K. Benkrid, D. Crookes, A. Benkrid","doi":"10.1109/CAMP.2003.1598160","DOIUrl":"https://doi.org/10.1109/CAMP.2003.1598160","url":null,"abstract":"Matrix multiplication is a core operation in digital signal processing operations with a variety of applications such as image processing, computer graphics, sonar processing and robotics. This paper presents the design and implementation of a high performance, fully parallel matrix multiplication core. The core is parameterised and scalable in terms of the matrices' dimensions (row and column number) and the input data word length. Fully floorplanned FPGA configurations are generated automatically, from high-level descriptions of the matrix multiplication operation, in the form of EDIF netlists in less than 1 sec. These are specifically optimised for Xilinx Virtex FPGA chips. By exploiting the abundance of logic resources in Xilinx Virtex FPGAs (look-up tables, fast carry logic, shift registers, flip flops etc.), a fully parallel implementation of the matrix multiplier core has been achieved; with a full matrix result being generated every clock cycle. A 3times3 matrix multiplier instance consumes 2,448 Virtex slices and can run at 175 MHz on an XCV1000E-6 Virtex-E chip, thus performing over 4.7 billion MAC/sec. This leads to 175 million full 3times3 matrix result per second","PeriodicalId":443821,"journal":{"name":"2003 IEEE International Workshop on Computer Architectures for Machine Perception","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124771479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Parallelisation of a face tracking algorithm with the SKiPPER-II parallel programming environment 基于SKiPPER-II并行编程环境的人脸跟踪算法并行化

2003 IEEE International Workshop on Computer Architectures for Machine Perception Pub Date : 2003-05-12 DOI: 10.1109/CAMP.2003.1598164

R. Coudarcher, F. Duculty, J. Sérot, F. Jurie, J. Derutin, M. Dhome

引用次数: 1

Real-time dense stereo on a personal computer 个人电脑上的实时密集立体声

2003 IEEE International Workshop on Computer Architectures for Machine Perception Pub Date : 2003-05-12 DOI: 10.1109/CAMP.2003.1598169

L. Di Stefano, M. Marchionni, S. Mattoccia

引用次数: 2