2019 IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA)最新文献

Improving SSD Performance Using Adaptive Restricted-Copyback Operations 使用自适应限制回拷操作提高SSD性能

2019 IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA) Pub Date : 2019-08-20 DOI: 10.1109/NVMSA.2019.8863524

Duwon Hong, Myungsuk Kim, Jisung Park, Myoungsoo Jung, Jihong Kim

引用次数: 7

NVMSA 2019 Message from the General Co-Chairs 2019年NVMSA总联合主席致辞

2019 IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA) Pub Date : 2019-08-01 DOI: 10.1109/nvmsa.2019.8863512

引用次数: 0

Host-Level Workload-Aware Budget Compensation I/O Scheduling for Open-Channel SSDs 开放通道ssd的主机级工作负载感知预算补偿I/O调度

2019 IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA) Pub Date : 2019-08-01 DOI: 10.1109/NVMSA.2019.8863515

Sooyun Lee, Kyuhwa Han, Dongkun Shin

引用次数: 1

Performance Evaluation on NVMM Emulator Employing Fine-Grain Delay Injection 采用细粒度延迟注入的NVMM仿真器性能评价

2019 IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA) Pub Date : 2019-08-01 DOI: 10.1109/NVMSA.2019.8863522

Yusuke Omori, K. Kimura

{"title":"Performance Evaluation on NVMM Emulator Employing Fine-Grain Delay Injection","authors":"Yusuke Omori, K. Kimura","doi":"10.1109/NVMSA.2019.8863522","DOIUrl":"https://doi.org/10.1109/NVMSA.2019.8863522","url":null,"abstract":"The emerging technology of byte-addressable nonvolatile memory chips is expected to enable larger main memory and lower power consumption than the traditional DRAM. It also realizes durable data structure without ordinary file systems. However, while enumerating the advantages of nonvolatile main memory (NVMM), its write-time expensive latency and higher energy consumption in comparision with a DRAM must be considered. These special characteristics of NVMM require new compiler techniques and OS support as well as new memory architectures. Several NVMM emulators built on real machines have been proposed to facilitate those software and hardware researches. Their designs were originally based on a simple coarse-grain delay model that injected additional clock cycles in the read and write requests sent to the memory controller. However, they could not utilize bank-level parallelism and row-buffer access locality, relied on by today’s memory modules, to exploit their performance. Therefore, a fine-grain delay model was recently proposed where the delay is injected for the primitive memory operations issued by the memory controller. In this paper, we implement both the coarse-grain and the fine-grain delay models on an SoC-FPGA board along with the use of Linux kernel modifications and several runtime functions. Then, the program behavior differences between two models are evaluated with SPEC CPU programs. The fine-grain model reveals the program execution time is influenced by the frequency of NVMM memory requests rather than the cache hit ratio. Bank-level parallelism and row-buffer access locality also affect the memory access delay, and the fine-grain model shows lower execution time for four of fourteen programs than the coarse-grain even when the former has longer total write latency.","PeriodicalId":438544,"journal":{"name":"2019 IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131266572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Optimizing Cauchy Reed-Solomon Coding via ReRAM Crossbars in SSD-based RAID Systems 在基于ssd的RAID系统中，通过ReRAM crossbar优化Cauchy Reed-Solomon编码

2019 IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA) Pub Date : 2019-08-01 DOI: 10.1109/NVMSA.2019.8863519

Lei Han, Shangzhen Tan, Bin Xiao, Chenlin Ma, Z. Shao

引用次数: 5

NVMSA 2019 Copyright Page NVMSA 2019版权页

2019 IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA) Pub Date : 2019-08-01 DOI: 10.1109/nvmsa.2019.8863509

引用次数: 0

NVMSA 2019 TOC

2019 IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA) Pub Date : 2019-08-01 DOI: 10.1109/nvmsa.2019.8863529

引用次数: 0

Fair Down to the Device: A GC-Aware Fair Scheduler for SSD 公平到设备:一个GC-Aware公平调度的SSD

2019 IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA) Pub Date : 2019-08-01 DOI: 10.1109/NVMSA.2019.8863523

Cheng Ji, Lun Wang, Qiao Li, Congming Gao, Liang Shi, Chia-Lin Yang, C. Xue

{"title":"Fair Down to the Device: A GC-Aware Fair Scheduler for SSD","authors":"Cheng Ji, Lun Wang, Qiao Li, Congming Gao, Liang Shi, Chia-Lin Yang, C. Xue","doi":"10.1109/NVMSA.2019.8863523","DOIUrl":"https://doi.org/10.1109/NVMSA.2019.8863523","url":null,"abstract":"Solid-state drives (SSD) are the mainstream solutions for massive data storage today. For modern computer systems, fair resource assignment is a critical design consideration and has drawn great interests in recent years. Although there are several I/O fairness schedulers proposed on the host side for SSDs, process fairness could still be dramatically degraded if garbage collection (GC) is triggered in the device side. A GC operation could block I/O requests, which causes unpredictable read/write latency variation and further impacts fairness between processes. This paper proposes Fair-GC, a novel coordinated host and device I/O scheduling strategy to achieve true fairness considering GC interferences. The key idea is to orchestrate GC operations inside SSDs carefully such that performance of a process is penalized by GC in the same degree (or comparable) as when it runs alone. In this way, the I/O fairness maintained by the host-side scheduler can be maintained in the presence of GC. Furthermore, our scheduler ensures that the timeslice of a process maintained at the host-side scheduler is updated in a timely manner to avoid unnecessary slowdown for maintaining fairness. Experimental results with a wide range of workloads verify that the proposed technique can achieve fairness as well as improve the throughput significantly. Compared to conventional fairness-based I/O scheduler, Fair-GC can reduce the slowdown of real applications by up to 99%, and improve the throughput by as much as 225%, respectively.","PeriodicalId":438544,"journal":{"name":"2019 IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA)","volume":"34 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114124724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A Memristor-based Scan Hold Flip-Flop 基于忆阻器的扫描保持触发器

2019 IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA) Pub Date : 2019-08-01 DOI: 10.1109/NVMSA.2019.8863517

Aijiao Cui, Zhenxing Chang, Ziming Wang, G. Qu, Huawei Li

引用次数: 2

fsync-aware Multi-Buffer FTL for Improving the fsync Latency with Open-Channel SSDs 基于fsync感知的多缓冲区FTL改进开放通道ssd的fsync延迟

2019 IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA) Pub Date : 2019-08-01 DOI: 10.1109/NVMSA.2019.8863514

Somm Kim, Yunji Kang, Dongkun Shin

引用次数: 1