发布求助
文献互助 智能选刊 最新文献

2nd International Conference on ASIC最新文献

筛选
英文 中文
New efficient design of digital comparator 新型高效的数字比较器设计
2nd International Conference on ASIC Pub Date : 1996-10-21 DOI: 10.1109/ICASIC.1996.562803
Wang Guangjie, Sheng Shimin, Ji Lijiu
{"title":"New efficient design of digital comparator","authors":"Wang Guangjie, Sheng Shimin, Ji Lijiu","doi":"10.1109/ICASIC.1996.562803","DOIUrl":"https://doi.org/10.1109/ICASIC.1996.562803","url":null,"abstract":"The digital comparator is a widely used circuit block. The typical versions using static CMOS logic have been well known. In this paper we present a new efficient design-MCP, which employs Manchester chain to fulfil the compare operation. Compared with the static implementations, MCP's highest operating frequency (125 MHz) is much higher. At the same operating frequency, MCP's power dissipation is 15%-22% lower than static version's. The layout area of MCP is only 87.6% of the static's and it is very convenient for implementing parallel or pipeline structure that is important for high performance VLSI design. By a series of optimizations the MCP gained a good noise immunity, though it is sensitive to noise glitches for its dynamic structure. MCP is a high quality function block and suitable for high performance VLSI design.","PeriodicalId":437663,"journal":{"name":"2nd International Conference on ASIC","volume":"355 Pt 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124263284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A TV graphics demonstration system design using FPGA 一个利用FPGA设计的电视图形演示系统
2nd International Conference on ASIC Pub Date : 1996-10-21 DOI: 10.1109/ICASIC.1996.562794
Li Qing, Li Wei, Yuanfang Xin, Xiao Ping, Hu Jingyu, Yang Liangxing
{"title":"A TV graphics demonstration system design using FPGA","authors":"Li Qing, Li Wei, Yuanfang Xin, Xiao Ping, Hu Jingyu, Yang Liangxing","doi":"10.1109/ICASIC.1996.562794","DOIUrl":"https://doi.org/10.1109/ICASIC.1996.562794","url":null,"abstract":"A TV graphics demonstration system is presented in this paper, which is a multimedia application based on PC, intended for home entertainment. The main functions of the system are graphics superimposing and screen capture. The system is implemented and verified by the PC-added video and graphics evaluating board.","PeriodicalId":437663,"journal":{"name":"2nd International Conference on ASIC","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125928608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Design and analysis of loop code recognition circuits 循环码识别电路的设计与分析
2nd International Conference on ASIC Pub Date : 1996-10-21 DOI: 10.1109/ICASIC.1996.562783
Ning Zhu, Yuanqing Ge, Rende Zhou, Xingzi Yang
{"title":"Design and analysis of loop code recognition circuits","authors":"Ning Zhu, Yuanqing Ge, Rende Zhou, Xingzi Yang","doi":"10.1109/ICASIC.1996.562783","DOIUrl":"https://doi.org/10.1109/ICASIC.1996.562783","url":null,"abstract":"This paper introduces the design of some circuits that can recognize loop code from an input code stream. The loop code in the stream can be arbitrary or a template specified by the user. We especially discuss the design method of these circuits, along with some simulation results.","PeriodicalId":437663,"journal":{"name":"2nd International Conference on ASIC","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117053637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analog design-for-testability for analog/mixed-signal ASICs 模拟/混合信号asic的可测试性设计
2nd International Conference on ASIC Pub Date : 1996-10-21 DOI: 10.1109/ICASIC.1996.562838
Guo-Nan Zhao
{"title":"Analog design-for-testability for analog/mixed-signal ASICs","authors":"Guo-Nan Zhao","doi":"10.1109/ICASIC.1996.562838","DOIUrl":"https://doi.org/10.1109/ICASIC.1996.562838","url":null,"abstract":"This paper discusses the concept and issues of Analog Design-for-Testability (ADFT) for analog/mixed-signal ASICs, and describes an algorithm for selecting the accessible nodes for excitation, a scheme for simplifying the ADFT with using of the macro-model circuit instead of the original circuit of the analog macros for including in ASIC chips, an architecture for a practically testable mixed-signal ASIC with using of MUXs and switching networks. Examples are illustrated to demonstrate the necessity of sufficient built-in accessible nodes for observability, the requirement of a few external directly accessible excitation terminals for controllability and the high demand of accuracy of measured test data besides the using of macromodel circuit for completeness in testing.","PeriodicalId":437663,"journal":{"name":"2nd International Conference on ASIC","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128660878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design and research of 8-bit Multiplier designed by maximum delay-difference stream-line processing 采用最大时延差分流线处理的8位乘法器的设计与研究
2nd International Conference on ASIC Pub Date : 1996-10-21 DOI: 10.1109/ICASIC.1996.562810
F. Youming, L. Weimin, Wan Da
{"title":"Design and research of 8-bit Multiplier designed by maximum delay-difference stream-line processing","authors":"F. Youming, L. Weimin, Wan Da","doi":"10.1109/ICASIC.1996.562810","DOIUrl":"https://doi.org/10.1109/ICASIC.1996.562810","url":null,"abstract":"An 8-bit Multiplier about the critical technology in parallel manipulating and high-performance processing was designed and manufactured in our laboratory. The suitable logic units and conversion were designed to decrease the disadvantageous effects of CMOS circuits effectively and raise circuit speed. Redundant inverter logic was used to adjust the length of the logic chains. The circuit was disunited into parts according to wafer structure and the characteristic of circuits. The logic simulation and post layout simulation were adapted to adjust the delay of logic chains.","PeriodicalId":437663,"journal":{"name":"2nd International Conference on ASIC","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123850021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Self-timed Booth's multiplier 自动计时布斯乘数
2nd International Conference on ASIC Pub Date : 1996-10-21 DOI: 10.1109/ICASIC.1996.562807
T. Pang, C. Choy, C. Chan, W. Cham
{"title":"Self-timed Booth's multiplier","authors":"T. Pang, C. Choy, C. Chan, W. Cham","doi":"10.1109/ICASIC.1996.562807","DOIUrl":"https://doi.org/10.1109/ICASIC.1996.562807","url":null,"abstract":"This paper presents some methods to improve the performance of an asynchronous system. Firstly, the structure of micropipeline, 2-phase and 4-phase handshake control protocol, asymmetrical delay element and delay selection circuit are discussed. Then we demonstrate how to use these circuit techniques to design the self-timed 8/spl times/8 Booth's multiplier. The performance of the circuit using these improvement techniques and different handshake control protocols are discussed and compared.","PeriodicalId":437663,"journal":{"name":"2nd International Conference on ASIC","volume":"65 Suppl 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121184136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
On fast exploration of ASIC design space 浅谈ASIC设计空间的快速探索
2nd International Conference on ASIC Pub Date : 1996-10-21 DOI: 10.1109/ICASIC.1996.562760
Z.X. Shen, C.C. Jong
{"title":"On fast exploration of ASIC design space","authors":"Z.X. Shen, C.C. Jong","doi":"10.1109/ICASIC.1996.562760","DOIUrl":"https://doi.org/10.1109/ICASIC.1996.562760","url":null,"abstract":"Ever-increasing microelectronics technology and market drive the ASICs more and more complex. Design space exploration become a crucial problem in high level synthesis. In this paper, an efficient precedence bipartite model and algorithms is proposed to explore the large design space. Experimental results show that with this model both the efficiency and the performance of synthesizing large digital system are greatly improved.","PeriodicalId":437663,"journal":{"name":"2nd International Conference on ASIC","volume":" 27","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113948989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An FPGA approach of channel decoder for DAB test receiver 一种用于DAB测试接收机信道解码器的FPGA实现方法
2nd International Conference on ASIC Pub Date : 1996-10-21 DOI: 10.1109/ICASIC.1996.562790
Jianxin Wang, Z. Dong
{"title":"An FPGA approach of channel decoder for DAB test receiver","authors":"Jianxin Wang, Z. Dong","doi":"10.1109/ICASIC.1996.562790","DOIUrl":"https://doi.org/10.1109/ICASIC.1996.562790","url":null,"abstract":"The Digital Audio Broadcasting (DAB) system promises to provide CD-quality sounds and flexible data services to mobile, portable and fixed receivers. In order to achieve high quality in multipath environment, a complicated channel coding and modulation scheme is adopted. This paper presents a channel decoding architecture for DAB test receiver, which accomplishes the functions including program selection, de-multiplexing, time de-interleaving, null symbol insertion into punctured bit-stream and Viterbi decoding. The channel decoder was successfully realized on field programmable gate arrays and Viterbi decoding chips.","PeriodicalId":437663,"journal":{"name":"2nd International Conference on ASIC","volume":"4171 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127565055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Low-power consumption architecture for embedded processor 嵌入式处理器的低功耗架构
2nd International Conference on ASIC Pub Date : 1996-10-21 DOI: 10.1109/ICASIC.1996.562755
Y. Yoshida, Bao-Yu Song, H. Okuhata, T. Onoye, I. Shirakawa
{"title":"Low-power consumption architecture for embedded processor","authors":"Y. Yoshida, Bao-Yu Song, H. Okuhata, T. Onoye, I. Shirakawa","doi":"10.1109/ICASIC.1996.562755","DOIUrl":"https://doi.org/10.1109/ICASIC.1996.562755","url":null,"abstract":"A low-power processor architecture is described dedicatedly for embedded application programs by means of an object code compression approach. This approach unifies duplicated instructions existing in the embedded program and assigns a simple number to each distinct instruction. An instruction decompressor is constructed in an embedded processor, which is to generate an object code from a compressed object code (pseudo code) input. A single-chip implementation of this decompressor together with a processor core can effectively reduce the bandwidth required for the I/O interface. Experiments are applied to an embedded processor ARMG10 to demonstrate the practicability of the proposed approach.","PeriodicalId":437663,"journal":{"name":"2nd International Conference on ASIC","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130184919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Design of a high speed cascaded sigma-delta ADC 高速级联σ - δ ADC的设计
2nd International Conference on ASIC Pub Date : 1996-10-21 DOI: 10.1109/ICASIC.1996.562802
Zhou Xiaofang, M. Hao, Lee Chen-Jung
{"title":"Design of a high speed cascaded sigma-delta ADC","authors":"Zhou Xiaofang, M. Hao, Lee Chen-Jung","doi":"10.1109/ICASIC.1996.562802","DOIUrl":"https://doi.org/10.1109/ICASIC.1996.562802","url":null,"abstract":"A high speed /spl Sigma//spl Delta/ ADC is designed for video application. A multi-bit cascaded /spl Sigma//spl Delta/ modulator is used to gain additional resolution under the oversampling rate of 4 or 8. Quantization errors are analyzed. Multi-stage halfband filters are used to remove the quantization error out of the base band. Simulation results are included.","PeriodicalId":437663,"journal":{"name":"2nd International Conference on ASIC","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114334492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信
小红书