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A Point-of-Care Device for Sensitive Protein Quantification 一种用于敏感蛋白定量的即时护理装置
2021 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2021-05-01 DOI: 10.1109/ISCAS51556.2021.9401643
F. Cavallo, K. B. Mirza, S. Mateo, J. Rodriguez-Manzano, K. Nikolic, C. Toumazou
{"title":"A Point-of-Care Device for Sensitive Protein Quantification","authors":"F. Cavallo, K. B. Mirza, S. Mateo, J. Rodriguez-Manzano, K. Nikolic, C. Toumazou","doi":"10.1109/ISCAS51556.2021.9401643","DOIUrl":"https://doi.org/10.1109/ISCAS51556.2021.9401643","url":null,"abstract":"In this paper we present the design of a new point-of-care device for protein quantification. The proposed design is based on a novel aptamer-mediated methodology and real time polymerase chain reaction (RT-PCR), a robust and ultrasensitive method for DNA amplification, which we employ for very sensitive quantification of proteins. In addition, we have also developed an algorithm for the processing of raw fluorescence data from the portable RT-PCR device. The algorithm leads to better linearity than a proprietary software from a commercially available RT-PCR machine. The modular nature of the system allows for easy assembly and adjustment towards a variety of biomarkers for applications in disease diagnosis and personalised medicine.","PeriodicalId":437127,"journal":{"name":"2021 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114663217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Delta-Sigma-Modulation Multi-Channel Network with Improved Noise-Shaping Characteristics 一种具有改进噪声整形特性的δ - σ调制多通道网络
2021 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2021-05-01 DOI: 10.1109/ISCAS51556.2021.9401511
T. Koizumi, T. Waho, H. Hayashi
{"title":"A Delta-Sigma-Modulation Multi-Channel Network with Improved Noise-Shaping Characteristics","authors":"T. Koizumi, T. Waho, H. Hayashi","doi":"10.1109/ISCAS51556.2021.9401511","DOIUrl":"https://doi.org/10.1109/ISCAS51556.2021.9401511","url":null,"abstract":"A delta-sigma-modulation multi-channel network is proposed for an analog-to-digital converter application. Weighting coefficients at summing nodes and digital filters obtaining the final output are designed so that adding the second channel cancels the first channel's quantization noise. The network suppresses the quantization noise leakage due to mismatch while improving the shaping characteristics. Increasing the weighting coefficients and the number of channels enhances the signal-to- noise ratio (SNR). Our signal-level simulation showed that for a 4-channel network, the SNR increased by around 25 dB, or an effective number of bits (ENOB) of 4 bits, compared with a 1-channel reference network for an oversampling ratio (OSR) of 60. Also, a preliminary circuit implementation demonstrated improved noise-shaping characteristics.","PeriodicalId":437127,"journal":{"name":"2021 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116633948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Novel Reservoir Computing Approach for the Detection of Chaos 一种新的混沌检测库计算方法
2021 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2021-05-01 DOI: 10.1109/ISCAS51556.2021.9401735
A. Ismail, S. Jovanovic, S. Petit-Watelot, H. Rabah
{"title":"Novel Reservoir Computing Approach for the Detection of Chaos","authors":"A. Ismail, S. Jovanovic, S. Petit-Watelot, H. Rabah","doi":"10.1109/ISCAS51556.2021.9401735","DOIUrl":"https://doi.org/10.1109/ISCAS51556.2021.9401735","url":null,"abstract":"Reservoir Computing (RC) is a novel framework for data computation extending from recurrent neural networks. The high dimensionality and flexibility of such processing paradigm make it well worthy for high complex systems analysis. Conceptor-driven Network (ConDN) is a RC-based paradigm whose unique structure is well appropriate for modelling and analysing multiple-input systems. In this paper, we present a ConDN approach for chaos detection in systems. Some known parametrizable systems exhibiting chaotic and non-chaotic behaviours have been analysed. By only observing the selected output results (trace matrix) after training of the ConDN method, the systems can be classified as chaotic or non-chaotic. In addition, the robustness of this method against white noise is also investigated.","PeriodicalId":437127,"journal":{"name":"2021 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116872937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Secure Mutual Authentication and Key-Exchange Protocol between PUF-Embedded IoT Endpoints 嵌入puf的物联网端点之间的安全互认证和密钥交换协议
2021 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2021-05-01 DOI: 10.1109/ISCAS51556.2021.9401135
Yue Zheng, Chip-Hong Chang
{"title":"Secure Mutual Authentication and Key-Exchange Protocol between PUF-Embedded IoT Endpoints","authors":"Yue Zheng, Chip-Hong Chang","doi":"10.1109/ISCAS51556.2021.9401135","DOIUrl":"https://doi.org/10.1109/ISCAS51556.2021.9401135","url":null,"abstract":"Device authentication and key exchange protocol are essential front line of access controls in IoT security, and physical unclonable function (PUF) is a key enabler to lightweight, low-power and secure authentication of internet enabled endpoint devices in IoT. Current PUF-enabled authentication protocol requires the verifier to store a sufficiently large number of challenge-response pairs (CRPs) of each of its interlocutors, which makes the protocol impractical in application scenarios where the verifier is a resource-constrained device, especially when the verifier needs to communicate with multiple PUF- embedded endpoints. To solve this problem, a new lightweight PUF-based mutual authentication and key-exchange protocol is proposed in this paper to allow two resource-constrained PUF embedded endpoint devices to authenticate each other without the need to store the CRPs locally, and simultaneously establish the session key for secure data exchange without resorting to public-key algorithm. The PUF response reliability is mitigated by the use of reverse fuzzy extractor to offload the compute- intensive error decoding to the server during the initialization phase of the protocol. The proposed protocol is evaluated using ProVerif to corroborate its secrecy, mutual authenticity as well as resistance against replay and man-in-the-middle attacks.","PeriodicalId":437127,"journal":{"name":"2021 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116938816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
A Stability Condition for Constant-On Time Buck Converters Suitable for Automotive Applications 适用于汽车应用的恒导时间降压变换器的稳定性条件
2021 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2021-05-01 DOI: 10.1109/ISCAS51556.2021.9401301
F. Bizzarri, L. Gardini, P. Nora, A. Brambilla
{"title":"A Stability Condition for Constant-On Time Buck Converters Suitable for Automotive Applications","authors":"F. Bizzarri, L. Gardini, P. Nora, A. Brambilla","doi":"10.1109/ISCAS51556.2021.9401301","DOIUrl":"https://doi.org/10.1109/ISCAS51556.2021.9401301","url":null,"abstract":"Approximate stability boundaries for Constant on- Time buck converters are derived and verified against numerical results obtained by bifurcation analysis. These boundaries are given as analytical expressions involving the main Constant on- Time (cot) buck converter parameters. They allow the designer to avoid the appearance of the pulse bursting phenomenon. A case study is proposed having in mind automotive applications, which are charaterized by a wide input-voltage range. The input- voltage and the output-capacitor equivalent series resistance, that is typically poorly controlled for many types of capacitors, were chosen as bifurcation parameters.","PeriodicalId":437127,"journal":{"name":"2021 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120949072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 10-b 500MS/s Partially Loop-Unrolled SAR ADC with a Comparator Offset Calibration Technique 采用比较器偏置校准技术的10-b 500MS/s部分环展开SAR ADC
2021 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2021-05-01 DOI: 10.1109/ISCAS51556.2021.9401439
Chao Chen, Jie Sun, Chenghua Wang, Weiqiang Liu
{"title":"A 10-b 500MS/s Partially Loop-Unrolled SAR ADC with a Comparator Offset Calibration Technique","authors":"Chao Chen, Jie Sun, Chenghua Wang, Weiqiang Liu","doi":"10.1109/ISCAS51556.2021.9401439","DOIUrl":"https://doi.org/10.1109/ISCAS51556.2021.9401439","url":null,"abstract":"This paper presents a 10-b 500MS/s successiveapproximation-register (SAR) analog-to-digital converter (ADC) designed using a 40nm CMOS process. The first 6-bit coarse conversion is completed by a high speed loop-unrolled architecture, while the succeeding 5 bits are obtained by a traditional SAR structure. A foreground calibration is employed to correct the offsets in the six comparators of the coarse converter, while the residual errors due to process-voltage-temperature (PVT) variations are covered by 1-bit redundancy. A background offset calibration technique based on alternate comparators is proposed, which tracks PVT variations while eliminating a dedicated calibration phase. The spurious-free-dynamic-range (SFDR) and the signal-to-noise-and-distortion-ratio (SNDR) can achieve 60.30dB and 68.95dBc, respectively. The power consumption of the whole system is 4.164mW under 1.1V supply voltage, thereby obtaining a figure of merit (FoM) of 9.87fJ/conv.-step.","PeriodicalId":437127,"journal":{"name":"2021 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124924888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Phase Domain Excess Loop Delay Compensation Technique with Latency Optimized Phase Selector for VCO-Based Continuous-Time ΔΣ ADC 基于vco的连续时间ΔΣ ADC的相位域过量环路延迟补偿技术
2021 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2021-05-01 DOI: 10.1109/ISCAS51556.2021.9401304
Yuekang Guo, J. Jin, Xiaoming Liu, Jianjun J. Zhou
{"title":"A Phase Domain Excess Loop Delay Compensation Technique with Latency Optimized Phase Selector for VCO-Based Continuous-Time ΔΣ ADC","authors":"Yuekang Guo, J. Jin, Xiaoming Liu, Jianjun J. Zhou","doi":"10.1109/ISCAS51556.2021.9401304","DOIUrl":"https://doi.org/10.1109/ISCAS51556.2021.9401304","url":null,"abstract":"This paper presents a phase domain excess loop delay compensation (ELDC) technique for voltage-controlled oscillator-based (VCO-based) continuous time (CT) ΔΣ ADC. The ELDC is achieved by shifting the phase of the sampling clock which composes a zero-order feedback loop in phase domain and avoid long latency between quantizer and DAC. The phase shifting is realized by a phase selector which selects the sampling clock from multi-phase clock signals generated by the phase interpolator. To ensure the stability of the ΔΣ ADC, a two-step phase selector is proposed to optimize the latency in the zero-order feedback loop. Simulation results shows that the proposed technique can effectively compensate ELD in phase domain and low latency feature in the feedback loop makes the technique suitable for high speed VCO-based CT ΔΣ ADC.","PeriodicalId":437127,"journal":{"name":"2021 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125038443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Body Channel Based Wireless Power Transfer Method for Implantable Bioelectronics 植入式生物电子学基于身体通道的无线能量传输方法
2021 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2021-05-01 DOI: 10.1109/ISCAS51556.2021.9401654
Cheng Han, Jingna Mao, Xuedi Wang, Shan Yu, Zhiwei Zhang
{"title":"Body Channel Based Wireless Power Transfer Method for Implantable Bioelectronics","authors":"Cheng Han, Jingna Mao, Xuedi Wang, Shan Yu, Zhiwei Zhang","doi":"10.1109/ISCAS51556.2021.9401654","DOIUrl":"https://doi.org/10.1109/ISCAS51556.2021.9401654","url":null,"abstract":"Implantable bioelectronics are becoming more widespread for biomedical applications. To avoid frequent surgical operations, self-powered implantable bioelectronics are more attractive. Traditional wireless power transfer (WPT) methods suffer from limitations that include bulky size, short transfer distance or flexibility limitation. In this paper, we present a new body channel based wireless power transfer (BC-WPT) method which uses the human body as power transfer medium to transfer power. In this way, the power receiver is only needed to be implanted in body tissue and the power transmitter can be applied on any part of the human body surface. Since the power transmitter and power receiver do not need a transmitting coil/antenna and a receiving coil/antenna, BC-WPT has the advantages of lower size, long transfer distance, and flexibility. A simulation platform and a prototype BC-WPT system are built to validate the availability of the proposed method.","PeriodicalId":437127,"journal":{"name":"2021 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125172174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Clonable PUF: on the Design of PUFs That Share Equivalent Responses 可克隆PUF:共享等效响应的PUF设计
2021 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2021-05-01 DOI: 10.1109/ISCAS51556.2021.9401345
Takashi Sato, Yuki Tanaka, S. Bian
{"title":"Clonable PUF: on the Design of PUFs That Share Equivalent Responses","authors":"Takashi Sato, Yuki Tanaka, S. Bian","doi":"10.1109/ISCAS51556.2021.9401345","DOIUrl":"https://doi.org/10.1109/ISCAS51556.2021.9401345","url":null,"abstract":"While numerous physically unclonable functions (PUFs) were proposed in recent years, the conventional PUF- based authentication model is centralized by the data of challenge-response pairs (CRPs), particularly when n-party authentication is required. In this work, we propose a novel concept of clonable PUF (CPUF), wherein two or more PUFs having equivalent responses are manufactured to facilitate decentralized authentication. By design, cloning is only possible in the fabrication period and the responses are determined based on the variability induced during the fabrication. We establish the usage model and the circuit design of CPUFs. Numerical experiments using a circuit simulator show an ideal matching rate of responses between the CPUFs.","PeriodicalId":437127,"journal":{"name":"2021 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125911743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Digitally Intensive Mixed-Signal Approach for Self-Interference Cancellation in LTE-A/5G-Transceivers LTE-A/ 5g收发器中数字密集混合信号自干扰消除方法
2021 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2021-05-01 DOI: 10.1109/ISCAS51556.2021.9401650
Oliver Ploder, C. Motz, T. Paireder, Christina Auer, H. Pretl, M. Huemer
{"title":"Digitally Intensive Mixed-Signal Approach for Self-Interference Cancellation in LTE-A/5G-Transceivers","authors":"Oliver Ploder, C. Motz, T. Paireder, Christina Auer, H. Pretl, M. Huemer","doi":"10.1109/ISCAS51556.2021.9401650","DOIUrl":"https://doi.org/10.1109/ISCAS51556.2021.9401650","url":null,"abstract":"State-of-the-art radio frequency transceivers for mobile communication devices suffer from transmitter-to-receiver (Tx-Rx) leakage in frequency division duplex operation, which, in combination with further non-idealities in the analog frontend, may lead to diverse self-interference (SI) effects. Digital as well as mixed-signal architectures have been proposed for self- interference cancellation. In this work we present a digitally intensive mixed-signal approach, where a low-cost auxiliary receiver senses the leaked Tx-signal. Firstly, the sensed signal is used to adaptively estimate the leakage channel, whereas in a second step a cleaned version of the leaked Tx-signal is reconstructed digitally. This reconstructed Tx-leakage signal is then used as input for a low complex adaptive interference cancellation unit to suppress modulated spurs or intermodulation distortions. We show that this approach allows to significantly relax the analog auxiliary receiver specifications, while different to conventional all-digital solutions being able to deal with multiple different types of SI with minimal configuration overhead.","PeriodicalId":437127,"journal":{"name":"2021 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123780738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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