2003 IEEE International Conference on Communications (Cat. No.03CH37441)最新文献

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Real-time L3 cache simulations using the Programmable Hardware-Assisted Cache Emulator (PHA$E) 使用可编程硬件辅助缓存模拟器(PHA$E)的实时L3缓存仿真

2003 IEEE International Conference on Communications (Cat. No.03CH37441) Pub Date : 2003-12-03 DOI: 10.1109/WWC.2003.1249060

Nirut Chalainanont, Eriko Nurvitadhi, R. Morrison, L. Su, K. Chow, Shih-Lien Lu, K. Lai

{"title":"Real-time L3 cache simulations using the Programmable Hardware-Assisted Cache Emulator (PHA$E)","authors":"Nirut Chalainanont, Eriko Nurvitadhi, R. Morrison, L. Su, K. Chow, Shih-Lien Lu, K. Lai","doi":"10.1109/WWC.2003.1249060","DOIUrl":"https://doi.org/10.1109/WWC.2003.1249060","url":null,"abstract":"As the gap between the CPU and memory speeds increases, there has been an increasingly important need to study the memory-hierarchy designs. Investigations of memory performance have typically been conducted using trace-driven simulation, which could take tremendous resources (e.g. long simulation time, large storage requirements for traces, and high overall cost). Recent works have proposed the use of hardware for performing cache simulations. Such approach is advantageous as it can be done in real-time, which eliminates the need or large storage for traces, reduces the simulation time, and improves the accuracy of the results. This paper discusses our preliminary work with theProgrammable Hardware-Assisted Cache Emulator (PHA$E), a system for emulating cache in real-time. We discuss the design and implementation of our system. Furthermore, the results of simulating varying sizes of off-chip L3 caches on various workloads (SPECcpu2000, SPECjbb2000, SPECjAppServer2002, and a large vocabulary continuous speech recognition system are presented and analyzed. Lastly, future research directions are elaborated on.","PeriodicalId":432745,"journal":{"name":"2003 IEEE International Conference on Communications (Cat. No.03CH37441)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122309193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

Improving the performance of OLTP workloads on SMP computer systems by limiting modified cache lines 通过限制修改的缓存线，提高SMP计算机系统上OLTP工作负载的性能

2003 IEEE International Conference on Communications (Cat. No.03CH37441) Pub Date : 2003-12-03 DOI: 10.1109/WWC.2003.1249054

J. Black, D. F. Wright, E. M. Salgueiro

{"title":"Improving the performance of OLTP workloads on SMP computer systems by limiting modified cache lines","authors":"J. Black, D. F. Wright, E. M. Salgueiro","doi":"10.1109/WWC.2003.1249054","DOIUrl":"https://doi.org/10.1109/WWC.2003.1249054","url":null,"abstract":"Symmetric multiprocessor (SMP) computer systems with more than four CPUs often exhibit significantly lower overall performance than would be expected from the sum of the performance of the individual CPUs. One of the causes of this degradation is the increased average memory latency due to cache to cache migration of modified cache lines. Such transfers often incur significantly longer latencies than a simple cache miss, which can be satisfied from main memory. By setting an upper bound on the number of modified cache lines that are allowed to exist in a main memory when this limit is exceeded, the average memory latency and overall system performance on an online transaction processing (OLTP) workload can be improved. This paper presents an investigation of this concept, called original limiting, on a commercial SMP system. The Original Limiting concept was implemented in the second level cache (SLC) of the Unisys NX6830 series of SMP systems, which support up to eight CPUs. An original limiting queue (OLQ) was added to limit the number of exclusive or modified lines in a 5% improvement in the number of transactions processed per minute, by reducing the average memory latency. A variety of experiments indicate that the OLQ is a simple, but effective, mechanism to enhance the performance of OLTP applications on SMP systems.","PeriodicalId":432745,"journal":{"name":"2003 IEEE International Conference on Communications (Cat. No.03CH37441)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126344505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

2003 IEEE International Workshop on Workload Characterization (IEEE Cat. No.03EX775) 2003年IEEE工作量表征国际研讨会(IEEE Cat)。No.03EX775)

2003 IEEE International Conference on Communications (Cat. No.03CH37441) Pub Date : 1900-01-01 DOI: 10.1109/wwc.2003.1249051

引用次数: 0

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