{"title":"Centralized Parallel form of Pattern Matching Algorithm in Packet Inspection by Efficient Utilization of Secondary Memory in Network Processor","authors":"N. Raja, K. Arulanandam, B. Rajarajeswari","doi":"10.5120/4951-7194","DOIUrl":"https://doi.org/10.5120/4951-7194","url":null,"abstract":"The network equipment has capable of inspecting packets in order to discover the worms and virus over the network. Many network users are hacked by attackers through malicious functions are mapped on network applications. Such unauthorized activities are required to delete by deep packet inspection in application layer. The high level network equipment provides in-depth packet inspection through pattern matching in network detection system. Researchers have developed high performance parallel deep packet filters for reconfigurable devices. Although some reconfigurable systems can be generated automatically from pattern database, obtaining high performance result from each subsequent reconfiguration can be a time consuming process. By presenting a novel architecture for programmable centralized parallel pattern matching algorithm for efficient packet inspection with network processor and coprocessor in order to retrieve the pattern with less time. Produce a hybrid system that is able to update the rules immediate during the time the new filter is being compiled reduction of resource-intensive task and increasing bandwidth used snort rule. . We mapped our centralized multi parallel pattern matching algorithm [CNMPPMA] for filter packet in parallel. The simulation result reveals that CNMPPMA significantly improves the matching performance. Also achieves the matching process with less cost.","PeriodicalId":428598,"journal":{"name":"Programmable Device Circuits and Systems","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-02-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115638993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"FPGA Implementation of Braun’s Multiplier Using Spartan-3E, Virtex – 4, Virtex-5 and Virtex-6","authors":"R. Anitha, V. Bagyaveereswaran","doi":"10.1007/978-3-642-22543-7_49","DOIUrl":"https://doi.org/10.1007/978-3-642-22543-7_49","url":null,"abstract":"","PeriodicalId":428598,"journal":{"name":"Programmable Device Circuits and Systems","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125109365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Simulation and Hardware Analysis of Three Phase PWM Rectifier for Power Factor Correction","authors":"P. Manikandan, S. Umayal, A. Mary","doi":"10.9790/1676-0812733","DOIUrl":"https://doi.org/10.9790/1676-0812733","url":null,"abstract":"Three-phase controlled rectifiers have a wide range of applications such as motor control in industries, dc drives, cycloconverters etc. They are used for electro-chemical process, many kinds of motor drives, traction equipment, controlled power supplies, and many other applications. The main aim of this paper is to design the three phase PWM rectifier and analyze its performance. The rectifier is designed to convert input ac power into intermediate dc power. This power conversion is done at unity power factor viewed from the supply mains. The advantage of this system is it also improves the power quality. This improved power factor improves/modifies the wave shape of line current close to sinusoidal and reduces the line amplitude of line current to reduces the line loss and hence to improve the power quality.","PeriodicalId":428598,"journal":{"name":"Programmable Device Circuits and Systems","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124219656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"PEARSON CORRELATION COEFFICIENT K-NEAREST NEIGHBOR OUTLIER CLASSIFICATION ON REAL-TIME DATASETS","authors":"D. Rajakumari, S. Karthika","doi":"10.21917/ijsc.2020.0290","DOIUrl":"https://doi.org/10.21917/ijsc.2020.0290","url":null,"abstract":"Detection and classification of data that do not meet the expected behavior (outliers) plays the major role in wide variety of applications such as military surveillance, intrusion detection in cyber security, fraud detection in on-line transactions. Nowadays, an accurate detection of outliers with high dimension is the major issue. The trade-off between the high-accuracy and low computational time is the major requirement in outlier prediction and classification. The presence of large size diverse features need the reduction mechanism prior to classification approach. To achieve this, the Distance-based Outlier Classification (DOC) is proposed in this paper. The proposed work utilizes the Pearson Correlation Coefficient (PCC) to measure the correlation between the data instances. The minimum instance learning through PCC estimation reduces the dimensionality. The proposed work is split up into two phases namely training and testing. During the training process, the labeling of most frequent samples isolates them from the infrequent reduce the data size effectively. The testing phase employs the k-Nearest Neighborhood (k-NN) scheme to classify the frequent samples effectively. The dimensionality and the k-value are inversely proportional to each other. In proposed work, the selection of large value of k offers the significant reduction in dimensionality. The combination of PCC-based instance learning and the high value of k reduces the dimensionality and noise respectively. The comparative analysis between the proposed PCC-k-NN with the conventional algorithms such as Decision Tree, Naive Bayes, Instance-Based K-means (IBK), Triangular Boundary-based Classification (TBC) regarding sensitivity, specificity, accuracy, precision, and recall proves its effectiveness in OC. Besides, the experimental validation of proposed PCC-k-NN with the state-of art methods regarding the execution time assures trade-off between the low-time consumption and high-accuracy.","PeriodicalId":428598,"journal":{"name":"Programmable Device Circuits and Systems","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131236238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}