2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT)最新文献_第3页

Discovering and understanding performance bottlenecks in transactional applications 发现并理解事务性应用程序中的性能瓶颈

2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2010-09-11 DOI: 10.1145/1854273.1854311

Ferad Zyulkyarov, Srdjan Stipic, T. Harris, O. Unsal, A. Cristal, I. Hur, M. Valero

引用次数: 39

Approximating age-based arbitration in on-chip networks 在片上网络中近似基于年龄的仲裁

2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2010-09-11 DOI: 10.1145/1854273.1854359

M. J. Lee, John Kim, D. Abts, Michael R. Marty, Jae W. Lee

引用次数: 6

SPACE: Sharing pattern-based directory coherence for multicore scalability SPACE:共享基于模式的目录一致性，实现多核可伸缩性

2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2010-09-11 DOI: 10.1145/1854273.1854294

Hongzhou Zhao, Arrvindh Shriraman, S. Dwarkadas

引用次数: 77

Ordered and unordered algorithms for parallel breadth first search 并行广度优先搜索的有序和无序算法

2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2010-09-11 DOI: 10.1145/1854273.1854341

M. A. Hassaan, Martin Burtscher, K. Pingali

引用次数: 7

System-level Max POwer (SYMPO) - a systematic approach for escalating system-level power consumption using synthetic benchmarks 系统级最大功率(SYMPO)——一种使用综合基准提高系统级功耗的系统方法

2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2010-09-11 DOI: 10.1145/1854273.1854282

K. Ganesan, Jungho Jo, W. Bircher, Dimitris Kaseridis, Zhibin Yu, L. John

{"title":"System-level Max POwer (SYMPO) - a systematic approach for escalating system-level power consumption using synthetic benchmarks","authors":"K. Ganesan, Jungho Jo, W. Bircher, Dimitris Kaseridis, Zhibin Yu, L. John","doi":"10.1145/1854273.1854282","DOIUrl":"https://doi.org/10.1145/1854273.1854282","url":null,"abstract":"To effectively design a computer system for the worst case power consumption scenario, system architects often use hand-crafted maximum power consuming benchmarks at the assembly language level. These stressmarks, also called power viruses, are very tedious to generate and require significant domain knowledge. In this paper, we propose SYMPO, an automatic SYstem level Max POwer virus generation framework, which maximizes the power consumption of the CPU and the memory system using genetic algorithm and an abstract workload generation framework. For a set of three ISAs, we show the efficacy of the power viruses generated using SYMPO by comparing the power consumption with that of MPrime torture test, which is widely used by industry to test system stability. Our results show that the usage of SYMPO results in the generation of power viruses that consume 14–41% more power compared to MPrime on SPARC ISA. The genetic algorithm achieved this result in about 70 to 90 generations in 11 to 15 hours when using a full system simulator. We also show that the power viruses generated in the Alpha ISA consume 9–24% more power compared to the previous approach of stressmark generation. We measure and provide the power consumption of these benchmarks on hardware by instrumenting a quad-core AMD Phenom II X4 system. The SYMPO power virus consumes more power compared to various industry grade power viruses on x86 hardware. We also provide a microarchitecture independent characterization of various industry standard power viruses.","PeriodicalId":422461,"journal":{"name":"2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125863323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 38

Tiled-MapReduce: Optimizing resource usages of data-parallel applications on multicore with tiling tile - mapreduce:通过平铺优化多核数据并行应用程序的资源使用

2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2010-09-11 DOI: 10.1145/1854273.1854337

Rong-Xin Chen, Haibo Chen, B. Zang

引用次数: 130

Energy efficient speculative threads: Dynamic thread allocation in same-ISA heterogeneous multicore systems 高能效推测线程:同一isa异构多核系统中的动态线程分配

2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2010-09-11 DOI: 10.1145/1854273.1854329

Yangchun Luo, Venkatesan Packirisamy, W. Hsu, Antonia Zhai

引用次数: 18

Adaptive spatiotemporal node selection in dynamic networks 动态网络中的自适应时空节点选择

2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2010-09-11 DOI: 10.1145/1854273.1854304

P. Hari, John B. P. McCabe, Jon Banafato, Marcus Henry, Kevin Ko, Emmanouil Koukoumidis, U. Kremer, M. Martonosi, L. Peh

引用次数: 3

Automatic vector instruction selection for dynamic compilation 动态编译的自动矢量指令选择

2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2010-09-11 DOI: 10.1145/1854273.1854358

R. Barik, Jisheng Zhao, Vivek Sarkar

引用次数: 6

Feedback-directed pipeline parallelism 反馈导向的管道并行性

2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2010-09-11 DOI: 10.1145/1854273.1854296

M. A. Suleman, Moinuddin K. Qureshi, Khubaib, Y. Patt

{"title":"Feedback-directed pipeline parallelism","authors":"M. A. Suleman, Moinuddin K. Qureshi, Khubaib, Y. Patt","doi":"10.1145/1854273.1854296","DOIUrl":"https://doi.org/10.1145/1854273.1854296","url":null,"abstract":"Extracting high performance from Chip Multiprocessors requires that the application be parallelized. A common software technique to parallelize loops is pipeline parallelism in which the programmer/compiler splits each loop iteration into stages and each stage runs on a certain number of cores. It is important to choose the number of cores for each stage carefully because the core-to-stage allocation determines performance and power consumption. Finding the best core-to-stage allocation for an application is challenging because the number of possible allocations is large, and the best allocation depends on the input set and machine configuration. This paper proposes Feedback-Directed Pipelining (FDP), a software framework that chooses the core-to-stage allocation at run-time. FDP first maximizes the performance of the workload and then saves power by reducing the number of active cores, without impacting performance. Our evaluation on a real SMP system with two Core2Quad processors (8 cores) shows that FDP provides an average speedup of 4.2x which is significantly higher than the 2.3x speedup obtained with a practical profile-based allocation. We also show that FDP is robust to changes in machine configuration and input set.","PeriodicalId":422461,"journal":{"name":"2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127070306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 64