发布求助
文献互助 智能选刊 最新文献

INA-OCMC '11最新文献

筛选
英文 中文
Emerging silicon photonics technologies for multi-core platform architectures 用于多核平台架构的新兴硅光子技术
INA-OCMC '11 Pub Date : 2011-01-23 DOI: 10.1145/1930037.1930038
L. Carloni
{"title":"Emerging silicon photonics technologies for multi-core platform architectures","authors":"L. Carloni","doi":"10.1145/1930037.1930038","DOIUrl":"https://doi.org/10.1145/1930037.1930038","url":null,"abstract":"The integration of emerging silicon photonics technologies with CMOS processes offers important advantages for the realization of scalable interconnection networks for both intra-chip and off-chip communication in next-generation multi-core computing platforms. The combination of electronic and optical communication technologies increases the number of architectural options to design both networks-on-chip and off-chip communication channels. The exploration of this broad design space requires the development of new models, methodologies, and tools to capture the physical and functional characteristics of photonic devices and enable their combination with electronic components to realize scalable and efficient interconnection networks. In this talk I will review recent progress in this research area by discussing the opportunities that are offered for system-level design and the challenges that remain to be addressed.","PeriodicalId":420489,"journal":{"name":"INA-OCMC '11","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123430493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A power-efficient network on-chip topology 低功耗的片上网络拓扑结构
INA-OCMC '11 Pub Date : 2011-01-23 DOI: 10.1145/1930037.1930044
J. Camacho, J. Flich, J. Duato, H. Eberle, Wladek Olesinski
{"title":"A power-efficient network on-chip topology","authors":"J. Camacho, J. Flich, J. Duato, H. Eberle, Wladek Olesinski","doi":"10.1145/1930037.1930044","DOIUrl":"https://doi.org/10.1145/1930037.1930044","url":null,"abstract":"NoCs have become a critical component in many-core architectures. Usually, the preferred topology is the 2D-Mesh as it enables a tile-based layout significantly reducing the design effort. However, new emerging challenges such as power consumption need to be addressed. Looking at the NoC, routers and links not being used must be switched off, thus achieving large power savings. Topology and routing algorithm must be carefully designed as they may lack enough flexibility to switch off components for long periods of time.\u0000 We present the NR-Mesh (Nearest neighboR Mesh) topology. It gives an end node the choice to inject a message through different neighboring routers, thereby reducing hop count and saving latency. At the receiver side, a message may be delivered to the end node through different routers, thus reducing hop count further and increasing flexibility. When allowing links and routers to switch off and combined with adaptive routing, the power management technique is able to achieve significant power savings (up to 36% savings in static power consumed at routers). When compared with the 2D-Mesh, NR-Mesh reduces execution time by 23% and power consumption at routers by 47%.","PeriodicalId":420489,"journal":{"name":"INA-OCMC '11","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126284785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Abstract modelling of switching elements for optical networks-on-chip with technology platform awareness 具有技术平台意识的片上光网络交换元件的抽象建模
INA-OCMC '11 Pub Date : 2011-01-23 DOI: 10.1145/1930037.1930046
A. Parini, L. Ramini, G. Bellanca, D. Bertozzi
{"title":"Abstract modelling of switching elements for optical networks-on-chip with technology platform awareness","authors":"A. Parini, L. Ramini, G. Bellanca, D. Bertozzi","doi":"10.1145/1930037.1930046","DOIUrl":"https://doi.org/10.1145/1930037.1930046","url":null,"abstract":"This paper reports the lessons learned in the abstraction process of the behaviour of switching elements for optical networks-on-chip, resulting in technology-annotated abstract models for the SystemC modelling and simulation environment. The paper points out the key physical effects that a designer should be aware of to properly assess effectiveness and feasibility of photonic switching fabrics. Moreover, the sources of inaccuracy are analysed when composing models of basic optical devices into higher order switching structures. Finally, a technique for modelling optical links into the SystemC framework is presented, by leveraging the pre-existing channel constructs. The findings of this paper capitalize on an extensive validation effort of abstract simulation models with FDTD simulations.","PeriodicalId":420489,"journal":{"name":"INA-OCMC '11","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114868814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
An improved algorithm for slot selection in the Æthereal network-on-chip 一种改进的Æthereal片上网络插槽选择算法
INA-OCMC '11 Pub Date : 2011-01-23 DOI: 10.1145/1930037.1930040
R. Stefan, K. Goossens
{"title":"An improved algorithm for slot selection in the Æthereal network-on-chip","authors":"R. Stefan, K. Goossens","doi":"10.1145/1930037.1930040","DOIUrl":"https://doi.org/10.1145/1930037.1930040","url":null,"abstract":"The rapid development in the electronics industry leads to a design process dominated by time-to-market constraints. The balance is shifted from logic design to packaging of already existing IP which results in a search for solutions for interconnecting the IP blocks. Networks-on-chip allow the rapid development a scalable interconnect and with the use of Circuit switching they can also provide guarantees for the speed of communication between IPs. In the current paper we demonstrate an improvement in the allocation algorithms for a Time-Division-Multiplexing Circuit-Switching scheme. We prove our algorithm to be optimal and we find that it provides an improvement of up to 26.7% compared to the previously proposed algorithm. The gain is more attractive as it comes at no cost for the actual hardware implementation.","PeriodicalId":420489,"journal":{"name":"INA-OCMC '11","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122461455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Process scheduling for future multicore processors 未来多核处理器的进程调度
INA-OCMC '11 Pub Date : 2011-01-23 DOI: 10.1145/1930037.1930042
T. Xu, P. Liljeberg, H. Tenhunen
{"title":"Process scheduling for future multicore processors","authors":"T. Xu, P. Liljeberg, H. Tenhunen","doi":"10.1145/1930037.1930042","DOIUrl":"https://doi.org/10.1145/1930037.1930042","url":null,"abstract":"In this paper, we study and analyze process scheduling problems for future multicore processors. It is expected that hundreds or even thousands of cores will be integrated on a single chip, known as a Chip Multiprocessor (CMP). However, operating system process scheduling, one of the most important design issues for CMP systems, has not been well addressed. We define a model for future CMPs, based on which a scheduling algorithm is proposed to reduce on-chip communication latencies and improve performance. The impact of memory access and inter process communication (IPC) in scheduling are analyzed. We explore six typical core allocation strategies. Results show that, a strategy with a balanced consideration of both IPC and memory access out-performs other strategies, the two metrics (misses per thousand instructions and cache hit latencies) are reduced up to 25.97% and 13.11%, respectively.","PeriodicalId":420489,"journal":{"name":"INA-OCMC '11","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130865422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Mesochronous NoC technology for power-efficient GALS MPSoCs 用于高能效GALS mpsoc的中同步NoC技术
INA-OCMC '11 Pub Date : 2011-01-23 DOI: 10.1145/1930037.1930045
D. Ludovici, Alessandro Strano, G. Gaydadjiev, D. Bertozzi
{"title":"Mesochronous NoC technology for power-efficient GALS MPSoCs","authors":"D. Ludovici, Alessandro Strano, G. Gaydadjiev, D. Bertozzi","doi":"10.1145/1930037.1930045","DOIUrl":"https://doi.org/10.1145/1930037.1930045","url":null,"abstract":"MPSoCs are today frequently designed as the composition of multiple voltage/frequency islands, thus calling for a GALS clocking style. In this context, the on-chip interconnection network can be either inferred as a single and independent clock domain or it can be distributed among core's domains. This paper targets the former scenario, since it results in the homogeneous speed of the NoC switching elements. From a physical design viewpoint, the main issues lie however in the chip-wide extension of the network domain and in the growing uncertainties affecting nanoscale silicon technologies. This paper proves that partitioning the network into mesochronous domains and merging synchronizers with NoC building blocks, two main advantages can be achieved. First, it is possible to evolve synchronous networks to mesochronous ones with marginal performance and area overhead. Second, the mesochronous NoC exposes more degrees of freedom for power optimization.","PeriodicalId":420489,"journal":{"name":"INA-OCMC '11","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134638388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
iFDOR: dynamic rerouting on-chip iFDOR:片上动态路由
INA-OCMC '11 Pub Date : 2011-01-23 DOI: 10.1145/1930037.1930041
F. Sem-Jacobsen, Samuel Rodrigo, T. Skeie
{"title":"iFDOR: dynamic rerouting on-chip","authors":"F. Sem-Jacobsen, Samuel Rodrigo, T. Skeie","doi":"10.1145/1930037.1930041","DOIUrl":"https://doi.org/10.1145/1930037.1930041","url":null,"abstract":"Many-core chip design requires flexible routing solutions for the interconnect to handle faults, provide performance partitions, and react to dynamic changes in processing requirements and power/heat distribution. We have developed a logic based rerouting mechanism suitable for tolerating dynamic powering down of regions within the application partition on the chip. This mechanism is combined with the logic based FDOR routing algorithm to create a powerful routing algorithm with low implementation cost. This allows for higher system utilisation through enabling more efficient power management as well as supporting many irregular mesh topologies through flexible virtualisation. Results show that powering down a single switch results in an 8% throughput reduction in the worst case for the evaluated topology.","PeriodicalId":420489,"journal":{"name":"INA-OCMC '11","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115532698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
EEEP: an extreme end to end flow control protocol for SDRAM access through networks on chip EEEP:一种极端的端到端流量控制协议，用于通过片上网络访问SDRAM
INA-OCMC '11 Pub Date : 2011-01-23 DOI: 10.1145/1930037.1930039
K. Hassan, F. Pétrot, R. Locatelli, M. Coppola
{"title":"EEEP: an extreme end to end flow control protocol for SDRAM access through networks on chip","authors":"K. Hassan, F. Pétrot, R. Locatelli, M. Coppola","doi":"10.1145/1930037.1930039","DOIUrl":"https://doi.org/10.1145/1930037.1930039","url":null,"abstract":"MPSoC platforms face an increasing diversity of traffic requirements due to the interaction between cores. This interaction is driven by the applications run by the user, and leads to the coexistence of the best effort traffic and the guaranteed service traffic in the same platform. We propose Extreme End-to-End Protocol (EEEP) as a new end-to-end flow control protocol to access SDRAMs through a multiport memory controller in NoC-based MPSoCs. Our protocol considers the memory access within a system approach. It exploits the occupancy rate of the requests queue in the memory controller within the policy of the traffic injection at the master Network Interfaces (NIs) level. By controlling the best-effort traffic shape, EEEP improves the bandwidth and the latency of the guaranteed service traffic.","PeriodicalId":420489,"journal":{"name":"INA-OCMC '11","volume":"206 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123617082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Switch allocator for bufferless network-on-chip routers 无缓冲片上网络路由器的开关分配器
INA-OCMC '11 Pub Date : 2011-01-23 DOI: 10.1145/1930037.1930043
G. Dimitrakopoulos, K. Galanopoulos
{"title":"Switch allocator for bufferless network-on-chip routers","authors":"G. Dimitrakopoulos, K. Galanopoulos","doi":"10.1145/1930037.1930043","DOIUrl":"https://doi.org/10.1145/1930037.1930043","url":null,"abstract":"Bufferless switches can be an attractive and energy-efficient design option for on-chip networks when network utilization is low and low-latency operation matters the most. However, this promising design option is limited by the complexity of the control logic required to operate a bufferless switch that imposes large delays and limits the clock frequency. Pipelining is not an option in this low-latency environment. In this paper, we propose a new switch allocator for bufferless switches that parallelizes the steps required for achieving a match between requesting inputs and available outputs and offers significantly faster implementations.","PeriodicalId":420489,"journal":{"name":"INA-OCMC '11","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121990071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信