Switch allocator for bufferless network-on-chip routers

Abstract

Bufferless switches can be an attractive and energy-efficient design option for on-chip networks when network utilization is low and low-latency operation matters the most. However, this promising design option is limited by the complexity of the control logic required to operate a bufferless switch that imposes large delays and limits the clock frequency. Pipelining is not an option in this low-latency environment. In this paper, we propose a new switch allocator for bufferless switches that parallelizes the steps required for achieving a match between requesting inputs and available outputs and offers significantly faster implementations.