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2006 IEEE North-East Workshop on Circuits and Systems最新文献

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3-TFT active pixel sensor with correlated double sampling readout circuit for real-time medical x-ray imaging 具有相关双采样读出电路的3-TFT有源像素传感器，用于实时医学x射线成像
2006 IEEE North-East Workshop on Circuits and Systems Pub Date : 2006-11-30 DOI: 10.1109/NEWCAS.2006.250919
N. Safavian, G. Chaji, M. Z. Kabir, A. Nathan, J. Rowlands
{"title":"3-TFT active pixel sensor with correlated double sampling readout circuit for real-time medical x-ray imaging","authors":"N. Safavian, G. Chaji, M. Z. Kabir, A. Nathan, J. Rowlands","doi":"10.1109/NEWCAS.2006.250919","DOIUrl":"https://doi.org/10.1109/NEWCAS.2006.250919","url":null,"abstract":"This paper presents a current-programmed, current-output active pixel sensor (APS) suitable for real time X-ray imaging (e.g., fluoroscopy) using hydrogenated amorphous silicon (a-Si:H) thin film transistor (TFT) technology and an appropriate CMOS readout circuit. The proposed pixel circuit can successfully compensate for characteristic variations such as mobility and threshold voltage shift in a-Si:H TFTs. The proposed readout circuit exploits correlated double sampling (CDS) technique not only for reducing the offset current and low frequency noise, but also to reduce the effect of fixed-pattern noise (FPN) on the array operation. The on-pixel amplification reduces the input referred noise to levels that can satisfy the strict requirements for low noise digital fluoroscopy","PeriodicalId":412640,"journal":{"name":"2006 IEEE North-East Workshop on Circuits and Systems","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122097910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The MLCA: A Solution Paradigm for Parallel Programmable SoCs MLCA:并行可编程soc的解决范例
2006 IEEE North-East Workshop on Circuits and Systems Pub Date : 2006-11-30 DOI: 10.1109/NEWCAS.2006.250944
T. Abdelrahman, A. Abdelkhalek, U. Aydonat, D. Capalija, D. Han, I. Matosevic, K. Stewart, F. Karim, A. Mellan
{"title":"The MLCA: A Solution Paradigm for Parallel Programmable SoCs","authors":"T. Abdelrahman, A. Abdelkhalek, U. Aydonat, D. Capalija, D. Han, I. Matosevic, K. Stewart, F. Karim, A. Mellan","doi":"10.1109/NEWCAS.2006.250944","DOIUrl":"https://doi.org/10.1109/NEWCAS.2006.250944","url":null,"abstract":"Parallel programmable systems-on-a-chip (PP-SoC) are quickly becoming the de facto architecture for high-performance embedded systems. The programming of these systems is a challenge that often increases the cost of system development. The multi-level computing architecture (MLCA) promises to address this programmability challenge by supporting a superscalar coarse-grain parallel programming model. In this paper, we describe the MLCA and its programming model. We provide an overview of the compilation environment we are developing for this architecture. We present an evaluation of the MLCA and its compiler support using realistic multimedia applications on a simulator and on an FPGA prototype of the MLCA. The results indicate the viability of this architecture for multimedia applications","PeriodicalId":412640,"journal":{"name":"2006 IEEE North-East Workshop on Circuits and Systems","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134066293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Low-Cost Stable a-Si:H AMOLED Display for Portable Applications 用于便携式应用的低成本稳定a-Si:H AMOLED显示器
2006 IEEE North-East Workshop on Circuits and Systems Pub Date : 2006-11-30 DOI: 10.1109/NEWCAS.2006.250909
G. Reza Chaji, A. Nathan
{"title":"Low-Cost Stable a-Si:H AMOLED Display for Portable Applications","authors":"G. Reza Chaji, A. Nathan","doi":"10.1109/NEWCAS.2006.250909","DOIUrl":"https://doi.org/10.1109/NEWCAS.2006.250909","url":null,"abstract":"A large sector of display market comprises portable devices including cell phones, personal organizers, PDAs, portable electronic games, etc. Important design considerations for displays employed in these applications are power consumption and cost. Hydrogenated Amorphous silicon (a-Si:H) active matrix organic light emitting diode (AMOLED) displays are promising technology for these applications. However, the a-Si:H AMOLED backplane suffers from the temporal instability. Although, several stable driving schemes have been proposed, they suffer from high implementation cost due to extra driving circuitry and high power consumption due to additional operating cycles. This paper presents a new driving scheme that provides a stable AMOLED display despite the aging effects in the a-Si:H thin film transistors and OLED, without increasing the driving complexity","PeriodicalId":412640,"journal":{"name":"2006 IEEE North-East Workshop on Circuits and Systems","volume":"174 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124262944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A New Fast Facial Recognition Algorithm Applicable to Large Databases 一种适用于大型数据库的快速人脸识别新算法
2006 IEEE North-East Workshop on Circuits and Systems Pub Date : 2006-11-30 DOI: 10.1109/NEWCAS.2006.250916
M. Abdelwahab, W. Mikhael
{"title":"A New Fast Facial Recognition Algorithm Applicable to Large Databases","authors":"M. Abdelwahab, W. Mikhael","doi":"10.1109/NEWCAS.2006.250916","DOIUrl":"https://doi.org/10.1109/NEWCAS.2006.250916","url":null,"abstract":"In this contribution, a transform domain two-dimensional principal component analysis algorithm employing vector quantization (TD2DPCA/VQ) is presented for facial recognition, particularly for large databases. The algorithm has attractive properties with respect to storage requirements in the training mode and the computational complexity in the testing mode. The experimental results obtained by applying the new algorithm to the ORL database confirmed the significant reduction in the storage and computational requirements while improving the excellent recognition accuracy of the spatial 2DPCA method","PeriodicalId":412640,"journal":{"name":"2006 IEEE North-East Workshop on Circuits and Systems","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124428809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A Digital Time Delay Measurement Technique and Phase-Locked Loop Requirements in a Standard CMOS Process 标准CMOS工艺中的数字时延测量技术及锁相环要求
2006 IEEE North-East Workshop on Circuits and Systems Pub Date : 2006-11-30 DOI: 10.1109/NEWCAS.2006.250964
T. Wey, B. Young
{"title":"A Digital Time Delay Measurement Technique and Phase-Locked Loop Requirements in a Standard CMOS Process","authors":"T. Wey, B. Young","doi":"10.1109/NEWCAS.2006.250964","DOIUrl":"https://doi.org/10.1109/NEWCAS.2006.250964","url":null,"abstract":"A digital architecture is proposed for measuring time delay increments much smaller than the clock period of a practical operating speed in a standard CMOS process. The technique employs correlated double sampling (CDS), a time-interleaved finite impulse response (FIR) averaging and infinite impulse response (IIR) noise filtering. A system with 200ns peak to peak delay deviation and 10-bit resolution requirement is presented in a 0.5mum CMOS process with an area estimate of 3.5 mm2 and power estimate of 60 mW","PeriodicalId":412640,"journal":{"name":"2006 IEEE North-East Workshop on Circuits and Systems","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124635764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Digital Encoders for High Speed Flash-ADCs: Modeling and Comparison 高速闪存adc的数字编码器:建模和比较
2006 IEEE North-East Workshop on Circuits and Systems Pub Date : 2006-11-30 DOI: 10.1109/NEWCAS.2006.250923
S. Masood Ali, R. Raut, M. Sawan
{"title":"Digital Encoders for High Speed Flash-ADCs: Modeling and Comparison","authors":"S. Masood Ali, R. Raut, M. Sawan","doi":"10.1109/NEWCAS.2006.250923","DOIUrl":"https://doi.org/10.1109/NEWCAS.2006.250923","url":null,"abstract":"Digital encoders are a known bottleneck for high speed flash-ADC architectures. This paper describes a survey of various thermometer-to-binary code (TC-to-BC) decoders. Wallace tree decoder is found to be the best among others in terms of bubble error correction but it consumes more power for multigiga hertz applications. Authors present that TC-to-BC decoder based on feedforward neural network structure cascaded with bit-swapping technique can achieve almost same level of performance for bubble error correction and consumes less power. The proposed implementation is suitable for CMOS process technology which is considered very economic solution in integrated circuits (IC) process industry","PeriodicalId":412640,"journal":{"name":"2006 IEEE North-East Workshop on Circuits and Systems","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128421835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Memory Access Patterns for the Analysis of MPSoCs 用于mpsoc分析的内存访问模式
2006 IEEE North-East Workshop on Circuits and Systems Pub Date : 2006-11-30 DOI: 10.1109/NEWCAS.2006.250943
S. Schliecker, M. Ivers, R. Ernst
{"title":"Memory Access Patterns for the Analysis of MPSoCs","authors":"S. Schliecker, M. Ivers, R. Ernst","doi":"10.1109/NEWCAS.2006.250943","DOIUrl":"https://doi.org/10.1109/NEWCAS.2006.250943","url":null,"abstract":"Unlike distributed systems, multiprocessor systems-on-chip often cannot integrate all memory needed for high performance applications within each processor. Hence, accesses to instruction and data memory use the same communication infrastructure as communication between processes. In this paper, we give an overview on an approach to analyze system timing in the presence of memory and coprocessor accesses in MpSoC systems and present a method to derive safe bounds on the traffic generated by tasks as well as resources with multiple tasks mapped to it","PeriodicalId":412640,"journal":{"name":"2006 IEEE North-East Workshop on Circuits and Systems","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127842751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Impact of Technology Scaling on the Performance of All-Time-On Single-Ended CMOS Logic 技术缩放对全天候单端CMOS逻辑性能的影响
2006 IEEE North-East Workshop on Circuits and Systems Pub Date : 2006-11-30 DOI: 10.1109/NEWCAS.2006.250941
Y. Abdalla, M. Elmasry
{"title":"Impact of Technology Scaling on the Performance of All-Time-On Single-Ended CMOS Logic","authors":"Y. Abdalla, M. Elmasry","doi":"10.1109/NEWCAS.2006.250941","DOIUrl":"https://doi.org/10.1109/NEWCAS.2006.250941","url":null,"abstract":"A qualitative analysis of the impact of technology scaling on the performance of all-time-on single-ended CMOS logic and MOS current mode logic (MCML) is presented. The analysis explains that the all-time-on CMOS single-ended logic is a strong competent to MCML at high speeds in current technology and also in future technology generations. Simulation results of a 4:1 MUX and a 1:4 DEMUX designed using either design techniques in different technology generations are provided in order to elucidate the impact of technology generations on the performance of either design techniques","PeriodicalId":412640,"journal":{"name":"2006 IEEE North-East Workshop on Circuits and Systems","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121153944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Distributed Current Mode Logic 分布式电流模式逻辑
2006 IEEE North-East Workshop on Circuits and Systems Pub Date : 2006-11-30 DOI: 10.1109/NEWCAS.2006.250939
S. Ardalan, K. Moez, M. Sachdev, M. Elmasry
{"title":"Distributed Current Mode Logic","authors":"S. Ardalan, K. Moez, M. Sachdev, M. Elmasry","doi":"10.1109/NEWCAS.2006.250939","DOIUrl":"https://doi.org/10.1109/NEWCAS.2006.250939","url":null,"abstract":"This paper introduces a new high-speed CMOS logic family called distributed current mode logic (DCML). This architecture is a combination of existing current mode logic (CML) architecture and the concept of distributed circuits. Distributed current mode logic takes advantages of distributed circuit, and is able to work up to 80 GHz in 0.13 mum CMOS technology. Because of the low noise behavior of the current mode logic family, DCML generates low power/substrate noise. Differential implementation of this logic makes it more immune to the noise generated by other blocks. These properties make this architecture a good candidate for very high-speed data communication integrated circuits","PeriodicalId":412640,"journal":{"name":"2006 IEEE North-East Workshop on Circuits and Systems","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122390400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Distributed Filtering of Unwanted Signals in Nonlinear Transmission Line Harmonic Generators and Mixers 非线性传输线谐波发生器和混频器中不需要信号的分布式滤波
2006 IEEE North-East Workshop on Circuits and Systems Pub Date : 2006-11-30 DOI: 10.1109/NEWCAS.2006.250930
K. Payandehjoo, R. Abhari
{"title":"Distributed Filtering of Unwanted Signals in Nonlinear Transmission Line Harmonic Generators and Mixers","authors":"K. Payandehjoo, R. Abhari","doi":"10.1109/NEWCAS.2006.250930","DOIUrl":"https://doi.org/10.1109/NEWCAS.2006.250930","url":null,"abstract":"Harmonic generation and wideband distributed mixing by using a nonlinear transmission line is presented. Distributed filtering by periodic loading of the NLTL with resonant circuits is proposed to reject the unwanted signals. A novel method for predicting the stopband of the filter by using the Floquet analysis is proposed in this paper. Circuit simulations are conducted utilizing a harmonic balance simulator. The suggested filtering technique is applied to a frequency doubler to provide a cleaner output signal and to a NLTL mixer for image rejection","PeriodicalId":412640,"journal":{"name":"2006 IEEE North-East Workshop on Circuits and Systems","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122632261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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