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Proceedings of 4th International Workshop on Hardware/Software Co-Design. Codes/CASHE '96最新文献

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Embedded architecture co-synthesis and system integration 嵌入式架构协同综合与系统集成
Proceedings of 4th International Workshop on Hardware/Software Co-Design. Codes/CASHE '96 Pub Date : 1996-03-18 DOI: 10.1109/HCS.1996.492220
Bill Lin, S. Vercauteren, H. Man
{"title":"Embedded architecture co-synthesis and system integration","authors":"Bill Lin, S. Vercauteren, H. Man","doi":"10.1109/HCS.1996.492220","DOIUrl":"https://doi.org/10.1109/HCS.1996.492220","url":null,"abstract":"Embedded system architectures comprising of software programmable components (e.g. DSP, ASIP, and micro-controller cores) and customized hardware co-processors, integrated into a single cost-efficient VLSI chip, are emerging as a key solution to today's microelectronics design problems. This trend is being driven by new emerging applications in the areas of wireless communication, high-speed optical networking, and multimedia computing. A key problem confronted by embedded system designers today is the rapid prototyping of application-specific embedded system architectures where different combinations of programmable processors and hardware components must be integrated together, while ensuring that the hardware and software parts communicate correctly. In this paper, we present a solution to this embedded architecture co-synthesis and system integration problem based on an orchestrated combination of architectural strategies, parameterized libraries, and software CAD tools.","PeriodicalId":412077,"journal":{"name":"Proceedings of 4th International Workshop on Hardware/Software Co-Design. Codes/CASHE '96","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129829416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Process partitioning for distributed embedded systems 分布式嵌入式系统的进程分区
Proceedings of 4th International Workshop on Hardware/Software Co-Design. Codes/CASHE '96 Pub Date : 1996-03-18 DOI: 10.1109/HCS.1996.492228
J. Hou, W. Wolf
{"title":"Process partitioning for distributed embedded systems","authors":"J. Hou, W. Wolf","doi":"10.1109/HCS.1996.492228","DOIUrl":"https://doi.org/10.1109/HCS.1996.492228","url":null,"abstract":"We present a new technique for partitioning processes in distributed embedded systems. Our heuristic algorithm minimizes both context switch and communication overhead under real-time deadline and process size constraints; it also tries to allocate functions to processors which are well-suited to that function. The algorithm analyzes the sensitivity of the latency of the task graph to changes in vertices hierarchical clustering, splitting and border adjusting. This algorithm can be used for initial partitioning during co-synthesis of distributed embedded systems. Synthesis of examples partitioned by our algorithm with implementations synthesized directly from the original example shows that our partitioning algorithm significantly improves the results obtainable by practical co-synthesis algorithms.","PeriodicalId":412077,"journal":{"name":"Proceedings of 4th International Workshop on Hardware/Software Co-Design. Codes/CASHE '96","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114730294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 115
A case study in co-design of communication controllers 通信控制器协同设计的实例研究
Proceedings of 4th International Workshop on Hardware/Software Co-Design. Codes/CASHE '96 Pub Date : 1996-03-18 DOI: 10.1109/HCS.1996.492232
R. Gerndt
{"title":"A case study in co-design of communication controllers","authors":"R. Gerndt","doi":"10.1109/HCS.1996.492232","DOIUrl":"https://doi.org/10.1109/HCS.1996.492232","url":null,"abstract":"The main objective of our activities in the first place was the implementation of a number of communication controllers. Analyzing the high complexity of the designs a formalized design methodology became mandatory. To ease the design process we developed a co-design methodology that makes possible the implementation of highly complex real-time applications with comparable short design cycles. The outcome of hardware components satisfies all timing constraints that were imposed by protocol and the reactivity of the application. It also was of reasonable size.","PeriodicalId":412077,"journal":{"name":"Proceedings of 4th International Workshop on Hardware/Software Co-Design. Codes/CASHE '96","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123390108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A model for the coanalysis of hardware and software architectures 用于硬件和软件体系结构协同分析的模型
Proceedings of 4th International Workshop on Hardware/Software Co-Design. Codes/CASHE '96 Pub Date : 1996-03-18 DOI: 10.1109/HCS.1996.492231
F. Rose, T. Carpenter, Sanjaya Kumar, J. Shackleton, Todd Steeves Honeywell
{"title":"A model for the coanalysis of hardware and software architectures","authors":"F. Rose, T. Carpenter, Sanjaya Kumar, J. Shackleton, Todd Steeves Honeywell","doi":"10.1109/HCS.1996.492231","DOIUrl":"https://doi.org/10.1109/HCS.1996.492231","url":null,"abstract":"Successful multiprocessor system design for complex real-time embedded applications requires powerful and comprehensive, yet cost-effective, productive, and maintainable modeling. The multi-disciplinary, VHDL-based modeling library developed by the Honeywell Technology Center places heavy emphasis on multiprocessing and distributed communications. These models focus on detailed hardware performance analysis along with multiple abstraction levels for software representation and evaluation. This paper details the processor model which provides the key element for the coanalysis of hardware and software system architectures.","PeriodicalId":412077,"journal":{"name":"Proceedings of 4th International Workshop on Hardware/Software Co-Design. Codes/CASHE '96","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124166486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A framework for interactive analysis of timing constraints in embedded systems 嵌入式系统时序约束交互分析框架
Proceedings of 4th International Workshop on Hardware/Software Co-Design. Codes/CASHE '96 Pub Date : 1996-03-18 DOI: 10.1109/HCS.1996.492225
Rajesh K. Gupta
{"title":"A framework for interactive analysis of timing constraints in embedded systems","authors":"Rajesh K. Gupta","doi":"10.1109/HCS.1996.492225","DOIUrl":"https://doi.org/10.1109/HCS.1996.492225","url":null,"abstract":"An important goal of embedded system co-synthesis is to realize system designs under constraints on timing performance. We present applicable constraints and the notion of satisfiability of a given set of constraints. We describe a two-level system model that is useful for carrying out constraint analysis in presence of the timing and execution uncertainty inherent in embedded systems. We conclude by presenting a framework to determine constraint satisfiability and to interactively debug constraint violations. Examples are presented to show the utility of our approach.","PeriodicalId":412077,"journal":{"name":"Proceedings of 4th International Workshop on Hardware/Software Co-Design. Codes/CASHE '96","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124854058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Fully parallel hardware/software codesign for multi-dimensional DSP applications 完全并行的硬件/软件协同设计的多维DSP应用
Proceedings of 4th International Workshop on Hardware/Software Co-Design. Codes/CASHE '96 Pub Date : 1996-03-18 DOI: 10.1109/HCS.1996.492222
M. Sheliga, N. Passos, E. Sha
{"title":"Fully parallel hardware/software codesign for multi-dimensional DSP applications","authors":"M. Sheliga, N. Passos, E. Sha","doi":"10.1109/HCS.1996.492222","DOIUrl":"https://doi.org/10.1109/HCS.1996.492222","url":null,"abstract":"The design of multi-dimensional systems using hardware/software codesign allows a significant improvement in the development cycle. This paper presents a technique that enables a design to have arbitrarily high throughput by using multi-dimensional retiming techniques while adjusting the composition of hardware and multiple software elements in order to satisfy the area requirements. A multi-dimensional graph representing the problem is transformed and scheduled such that all nodes are executed in a fully parallel way. The techniques presented are applicable to any problem which can be represented as a multi-dimensional data flow graph. Results are shown which illustrate the efficiency of the system as well as the savings achieved.","PeriodicalId":412077,"journal":{"name":"Proceedings of 4th International Workshop on Hardware/Software Co-Design. Codes/CASHE '96","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121210662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Partitioning and exploration strategies in the TOSCA co-design flow TOSCA协同设计流中的划分和探索策略
Proceedings of 4th International Workshop on Hardware/Software Co-Design. Codes/CASHE '96 Pub Date : 1996-03-18 DOI: 10.1109/HCS.1996.492227
A. Balboni, W. Fornaciari, D. Sciuto
{"title":"Partitioning and exploration strategies in the TOSCA co-design flow","authors":"A. Balboni, W. Fornaciari, D. Sciuto","doi":"10.1109/HCS.1996.492227","DOIUrl":"https://doi.org/10.1109/HCS.1996.492227","url":null,"abstract":"The TOSCA environment for hardware/software co-design of control dominated systems implemented on a single chip includes a novel approach to the system exploration phase for the evaluation of alternative architectures. The paper presents the metrics and the partitioning algorithm defined for the identification of the best hardware and software bindings and modularization, given the design constraints and goals. The system exploration phase is implemented as an iterative process directed by the user, based on the formal internal design representation adopted in TOSCA. The application of the metrics is then shown on a simple example to illustrate the approach.","PeriodicalId":412077,"journal":{"name":"Proceedings of 4th International Workshop on Hardware/Software Co-Design. Codes/CASHE '96","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126141301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 57
A co-design methodology based on formal specification and high-level estimation 一种基于正式规范和高级评估的协同设计方法
Proceedings of 4th International Workshop on Hardware/Software Co-Design. Codes/CASHE '96 Pub Date : 1996-03-18 DOI: 10.1109/HCS.1996.492223
C. Carreras, J. C. López, M. Vallejo, L. Sánchez, C. D. Kloos, N. M. Madrid
{"title":"A co-design methodology based on formal specification and high-level estimation","authors":"C. Carreras, J. C. López, M. Vallejo, L. Sánchez, C. D. Kloos, N. M. Madrid","doi":"10.1109/HCS.1996.492223","DOIUrl":"https://doi.org/10.1109/HCS.1996.492223","url":null,"abstract":"This paper presents a methodology for hardware-software co-design. It is based on the formal description technique LOTOS in the specification phase, and on estimation methods at different levels of abstraction in the partitioning phase. The LOTOS specification describes the system as a set of interacting communicating processes. Our HW-SW partitioning algorithm is guided by communications, performance and area estimates and by the suitability of each process for implementation in hardware or software. A partition is evaluated against the design goals and constraints, first using high-level estimates and then if requirements are met, computing estimates at lower levels of abstraction. If the partition fails, the partitioning model is updated with the new, low-level estimates and a new partition is generated. If it succeeds, the resulting hardware and software specifications are synthesized using existing high-level synthesis tools and compilers.","PeriodicalId":412077,"journal":{"name":"Proceedings of 4th International Workshop on Hardware/Software Co-Design. Codes/CASHE '96","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122888134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
Towards a model for hardware and software functional partitioning 对硬件和软件的功能划分模型
Proceedings of 4th International Workshop on Hardware/Software Co-Design. Codes/CASHE '96 Pub Date : 1996-03-18 DOI: 10.1109/HCS.1996.492233
F. Vahid, T. D. Le
{"title":"Towards a model for hardware and software functional partitioning","authors":"F. Vahid, T. D. Le","doi":"10.1109/HCS.1996.492233","DOIUrl":"https://doi.org/10.1109/HCS.1996.492233","url":null,"abstract":"We describe a model that supports the functional partitioning of a system-level functional specification among hardware and software components. The model includes only the information needed by partitioning, and thus can be communicated freely and generated automatically. Based on characteristics of several real examples, we describe a technique for automatically generating generic model instances, on which partitioning heuristics can be applied and fairly compared. Such comparisons will become increasingly important as research begins to focus on fast yet effective functional partitioning techniques. We describe a set of tools for converting a specification to the model, for generating generic model instances, and for applying and comparing partitioning heuristics, available via ftp. Use of these tools may greatly reduce duplicated efforts among researchers wishing to investigate hardware/software partitioning heuristics.","PeriodicalId":412077,"journal":{"name":"Proceedings of 4th International Workshop on Hardware/Software Co-Design. Codes/CASHE '96","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127060712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
PACE: a dynamic programming algorithm for hardware/software partitioning PACE:一种用于硬件/软件分区的动态规划算法
Proceedings of 4th International Workshop on Hardware/Software Co-Design. Codes/CASHE '96 Pub Date : 1996-03-18 DOI: 10.1109/HCS.1996.492230
P. Knudsen, J. Madsen
{"title":"PACE: a dynamic programming algorithm for hardware/software partitioning","authors":"P. Knudsen, J. Madsen","doi":"10.1109/HCS.1996.492230","DOIUrl":"https://doi.org/10.1109/HCS.1996.492230","url":null,"abstract":"This paper presents the PACE partitioning algorithm which is used in the LYCOS co-synthesis system for partitioning control/dataflow graphs into hardware and software parts. The algorithm is a dynamic programming algorithm which solves both the problem of minimizing system execution time with a hardware area constraint and the problem of minimizing hardware area with a system execution time constraint. The target architecture consists of a single microprocessor and a single hardware chip (ASIC, FPGA, etc.) which are connected by a communication channel. The algorithm incorporates a realistic communication model and thus attempts to minimize communication overhead. The time-complexity of the algorithm is O(n/sup 2//spl middot//spl Ascr/) and the space-complexity is O(n/spl middot//spl Ascr/) where /spl Ascr/ is the total area of the hardware chip and n the number of code fragments which may be placed in either hardware or software.","PeriodicalId":412077,"journal":{"name":"Proceedings of 4th International Workshop on Hardware/Software Co-Design. Codes/CASHE '96","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127478122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 92
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