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IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems最新文献

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Scheduling policies for fault tolerance in a VLSI processor VLSI处理器中容错调度策略
IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1994-10-17 DOI: 10.1109/DFTVS.1994.630008
Yinan N. Shen, H. Kari, Sungsoo Kim, F. Lombardi
{"title":"Scheduling policies for fault tolerance in a VLSI processor","authors":"Yinan N. Shen, H. Kari, Sungsoo Kim, F. Lombardi","doi":"10.1109/DFTVS.1994.630008","DOIUrl":"https://doi.org/10.1109/DFTVS.1994.630008","url":null,"abstract":"This paper presents analytical and simulation models for evaluating the operation of a VLSI processor (in a uniprocessor configuration) which utilizes a time-redundant approach (such as recomputation by shifted operands) for fault-tolerant computing. In the proposed approach, all incoming jobs to the uniprocessor are duplicated, thus two versions of each job must be processed. A discrepancy in the results produced by comparing the outcomes of the two versions of the same job indicates that a fault may have occurred. Several methods for appropriately scheduling the primary and secondary versions of the jobs are proposed and analyzed.","PeriodicalId":409138,"journal":{"name":"IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126728772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Alternative approaches to fault detection in FSMs fsm故障检测的几种方法
IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1994-10-17 DOI: 10.1109/DFTVS.1994.630040
R. Leveugle, R. Rochet, G. Saucier
{"title":"Alternative approaches to fault detection in FSMs","authors":"R. Leveugle, R. Rochet, G. Saucier","doi":"10.1109/DFTVS.1994.630040","DOIUrl":"https://doi.org/10.1109/DFTVS.1994.630040","url":null,"abstract":"This paper addresses the detection of permanent or transient faults in complex VLSI circuits, with a particular focus on faults leading to sequencing errors. On-line test devices are automatically generated by a specific synthesis tool (ASYL-SdF), avoiding design time overhead. Two approaches based on control-flow checking methods are available to the designer and it is shown that each of these approaches leads, in some cases, to the cheapest implementation. In particular, noticeable gains can be obtained compared with the classical approach based on duplication.","PeriodicalId":409138,"journal":{"name":"IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127009432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Reconfiguration in 3D meshes 在3D网格中重新配置
IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1994-10-17 DOI: 10.1109/DFTVS.1994.630030
Anuj Chandra, R. Melhem
{"title":"Reconfiguration in 3D meshes","authors":"Anuj Chandra, R. Melhem","doi":"10.1109/DFTVS.1994.630030","DOIUrl":"https://doi.org/10.1109/DFTVS.1994.630030","url":null,"abstract":"The 1 1/2 track model for fault tolerant 2D processor arrays is extended to 3D mesh architectures. Non-intersecting, continuous, straight and non-near miss compensation paths are considered. It is shown that when six directions in the 3D mesh are allowed for compensation paths, then switches with 13 states are needed to preserve the 3D mesh topology after faults. It is also shown that switch reconfiguration after faults is local in the sense that the state of each switch is uniquely determined by the state of the processors connected to it.","PeriodicalId":409138,"journal":{"name":"IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"406 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116032888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
On soft switch programming for reconfigurable array systems 可重构阵列系统软交换编程研究
IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1994-10-17 DOI: 10.1109/DFTVS.1994.630031
Tong Liu, F. Lombardi
{"title":"On soft switch programming for reconfigurable array systems","authors":"Tong Liu, F. Lombardi","doi":"10.1109/DFTVS.1994.630031","DOIUrl":"https://doi.org/10.1109/DFTVS.1994.630031","url":null,"abstract":"This paper deals with the programming and control of non-permanent (soft) switching elements in an augmented interconnection network of a two-dimensional VLSI/WSI array. In particular, it is addressed the issue of cost for programming soft switches involved in the routing process for the interconnections from the primary pad pins. Cost is analyzed with respect to the complexity of the switches (as given by their switching modes) and the number of programming steps involved in establishing the desired interconnections.","PeriodicalId":409138,"journal":{"name":"IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130765111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A fault-tolerant associative approach to on-line memory repair 联机记忆修复的容错关联方法
IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1994-10-17 DOI: 10.1109/DFTVS.1994.630027
Jien-Chung Lo
{"title":"A fault-tolerant associative approach to on-line memory repair","authors":"Jien-Chung Lo","doi":"10.1109/DFTVS.1994.630027","DOIUrl":"https://doi.org/10.1109/DFTVS.1994.630027","url":null,"abstract":"A fault-tolerant associative approach is proposed to be used in on-line repair for highly available memories. The memory repair mechanism is designed similar to a cache memory in its spare to main memory mapping schemes. Four spare memory mapping schemes are presented: fully associative, associative direct, associative set and associative multiple. If cache memory repair is needed, the proposed schemes can also be applied. The repair mechanism consists of a TMR content addressable memory (CAM) and an SEC/DED spare data memory. Although it is sufficient to encode the CAM with SEC code, we find that TMR version is faster in accessing time and more cost-effective. To repair a 1M/spl times/32 main memory with eight spare words, the proposed schemes use less than 0.015% of hardware redundancy.","PeriodicalId":409138,"journal":{"name":"IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129190758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
On fractal yield models: a statistical paradox 分形产量模型:一个统计悖论
IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1994-10-17 DOI: 10.1109/DFTVS.1994.630017
C. Stapper, A. J. Rideout
{"title":"On fractal yield models: a statistical paradox","authors":"C. Stapper, A. J. Rideout","doi":"10.1109/DFTVS.1994.630017","DOIUrl":"https://doi.org/10.1109/DFTVS.1994.630017","url":null,"abstract":"Although the fractal yield model is very successful in VLSI applications, it also exposes a mathematical inconsistency. Expressing the average number of faults in each sub array, the average number of faults in the complete array, according to this approach, is not statistically correct. This, therefore, is a fractal paradox.","PeriodicalId":409138,"journal":{"name":"IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131278646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On the testability of CMOS feedback amplifiers CMOS反馈放大器的可测试性研究
IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1994-10-17 DOI: 10.1109/DFTVS.1994.630015
A. Bishop, A. Ivanov
{"title":"On the testability of CMOS feedback amplifiers","authors":"A. Bishop, A. Ivanov","doi":"10.1109/DFTVS.1994.630015","DOIUrl":"https://doi.org/10.1109/DFTVS.1994.630015","url":null,"abstract":"This paper examines the testability of a CMOS operational amplifier (op-amp) in four different feedback configurations. Feedback is often considered to complicate the testing problem. Here, we illustrate that it is possible to test the op-amp for catastrophic faults at wafer probe without having to remove feedback structures. Catastrophic, as well as parameter variation fault models, are used to simulate the faulty response of the opamp circuits. Our method relies on repeated Monte Carlo fault simulations to examine differences in a circuit's response for each possible fault condition. A sine wave is used for the test stimulus in each case. Four closed loop configurations are considered for the study: integrator, differentiator, inverting amplifier, and comparator. We tally the percentage of stuck-at, short, and open faults that are detectable with the feedback applied to demonstrate that the four feedback network configurations have little effect on the catastrophic fault coverage, as compared with similar tests performed for an open-loop configuration.","PeriodicalId":409138,"journal":{"name":"IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133221499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A CMOS fault tolerant architecture for switch-level faults 一种用于开关级故障的CMOS容错架构
IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1994-10-17 DOI: 10.1109/DFTVS.1994.630009
C. Bolchini, G. Buonanno, D. Sciuto, R. Stefanelli
{"title":"A CMOS fault tolerant architecture for switch-level faults","authors":"C. Bolchini, G. Buonanno, D. Sciuto, R. Stefanelli","doi":"10.1109/DFTVS.1994.630009","DOIUrl":"https://doi.org/10.1109/DFTVS.1994.630009","url":null,"abstract":"This paper presents the application of a new fault tolerant methodology to multiple output CMOS static gates. The adopted fault models include line stuck-at, transistor stuck-open, transistor stuck-on and bridging faults, thus covering a larger number of actual device faults than the simple line stuck-at fault model considered at gate level. The proposed approach is based on the encoding of the circuit outputs with Berger codes and by introducing additional networks to provide tolerance to single stuck-on faults and to a relevant number of multiple faults, also reducing to unidirectional faults (and thus detectable with Berger code) the class of not tolerated faults.","PeriodicalId":409138,"journal":{"name":"IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130791313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
An approach to the development of a Iddq testable cell library 一种开发Iddq可测试单元库的方法
IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1994-10-17 DOI: 10.1109/DFTVS.1994.630013
C. Ferrer, D. Dateo, J. Oliver, A. Rubio, M. Rullán
{"title":"An approach to the development of a Iddq testable cell library","authors":"C. Ferrer, D. Dateo, J. Oliver, A. Rubio, M. Rullán","doi":"10.1109/DFTVS.1994.630013","DOIUrl":"https://doi.org/10.1109/DFTVS.1994.630013","url":null,"abstract":"Many VLSI integrated circuit processing defects can cause changes in the behaviour of the quiescent power supply current. Testing techniques based on the quiescent power supply current inspection have been reported to be efficient in the detection of a wide range of physical defects. In this paper we present one approach to Iddq testing based on the application of BIC sensors to a cell library design methodology. The size of the sensor will depend on the length of the row as well as on the frequency of the circuit under test.","PeriodicalId":409138,"journal":{"name":"IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"242 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117165702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A yield study of VLSI adders VLSI加法器的良率研究
IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1994-10-17 DOI: 10.1109/DFTVS.1994.630035
Zhan Chen, I. Koren
{"title":"A yield study of VLSI adders","authors":"Zhan Chen, I. Koren","doi":"10.1109/DFTVS.1994.630035","DOIUrl":"https://doi.org/10.1109/DFTVS.1994.630035","url":null,"abstract":"Several 64-bit adders have been designed and their expected yield has been estimated. Our results show that the yield of VLSI adders can be improved by modifying the layout of the original design and/or by choosing a different layout and circuit structure. In certain situations, these approaches can improve the yield by 10% to 17%.","PeriodicalId":409138,"journal":{"name":"IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126380022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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