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Off-chip access localization for NoC-based multicores 基于网卡的多核的片外访问定位
2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370889
W. Ding, M. Kandemir, Yuanrui Zhang, Emre Kultursay
{"title":"Off-chip access localization for NoC-based multicores","authors":"W. Ding, M. Kandemir, Yuanrui Zhang, Emre Kultursay","doi":"10.1145/2370816.2370889","DOIUrl":"https://doi.org/10.1145/2370816.2370889","url":null,"abstract":"In a network-on-chip based multicore, an off-chip data access needs to travel through the on-chip network, spending considerable amount of time within the chip (in addition to the memory access itself). Further, it also causes additional delays for on-chip accesses by creating contention on network resources. In this paper, we propose a compiler-guided off-chip data access localization strategy to ensure that, an off-chip access traverses a small number of links (hops) to reach the memory controller which governs the memory bank that holds the requested data. The results collected clearly emphasize the importance of localizing off-chip accesses.","PeriodicalId":403855,"journal":{"name":"2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128988359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Application-aware prefetch prioritization in on-chip networks 片上网络中应用感知的预取优先级
2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370886
N. Nachiappan, Asit K. Mishra, M. Kandemir, A. Sivasubramaniam, O. Mutlu, C. Das
{"title":"Application-aware prefetch prioritization in on-chip networks","authors":"N. Nachiappan, Asit K. Mishra, M. Kandemir, A. Sivasubramaniam, O. Mutlu, C. Das","doi":"10.1145/2370816.2370886","DOIUrl":"https://doi.org/10.1145/2370816.2370886","url":null,"abstract":"Data prefetching is an effective technique for hiding memory latency. When issued prefetches are inaccurate, performance can degrade. Prior research provided solutions to deal with inaccurate prefetches at the cache and memory levels, but not in the interconnect of a large-scale multiprocessor system. This work introduces application-aware prefetch prioritization techniques to mitigate the negative effects of prefetching in a network-on-chip (NoC) based multicore system. The idea is to rank prefetches from different applications based on their potential utility for the application and propensity to cause interference to other applications. Our evaluation shows that this approach provides significant performance improvements over a baseline that does not distinguish between prefetches from different applications.","PeriodicalId":403855,"journal":{"name":"2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132532195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
PEPON: Performance-aware hierarchical power budgeting for NoC based multicores 基于NoC的多核性能感知分层功率预算
2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370828
Akbar Sharifi, Asit K. Mishra, Shekhar Srikantaiah, M. Kandemir, C. Das
{"title":"PEPON: Performance-aware hierarchical power budgeting for NoC based multicores","authors":"Akbar Sharifi, Asit K. Mishra, Shekhar Srikantaiah, M. Kandemir, C. Das","doi":"10.1145/2370816.2370828","DOIUrl":"https://doi.org/10.1145/2370816.2370828","url":null,"abstract":"Targeting NoC based multicores, we propose a two-level power budget distribution mechanism, called PEPON, where the first level distributes the overall power budget of the multicore system among various types of on-chip resources like the cores, caches, and NoC, and the second level determines the allocation of power to individual instances of each type of resource. Both these distributions are oriented towards maximizing workload performance without exceeding the specified power budget. Extensive experimental evaluations of the proposed power distribution scheme using a full system simulation and detailed power models emphasize the importance of power budget partitioning at both levels. Specifically, our results show that the proposed scheme can provide up to 29% performance improvement as compared to no power budgeting, and performs 13% better than a competing scheme, under the same chip-wide power cap.","PeriodicalId":403855,"journal":{"name":"2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132263278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
Using combined profiling to decide when Thread Level Speculation is profitable 使用组合分析来决定何时线程级别推测是有利可图的
2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370908
Arnamoy Bhattacharyya
{"title":"Using combined profiling to decide when Thread Level Speculation is profitable","authors":"Arnamoy Bhattacharyya","doi":"10.1145/2370816.2370908","DOIUrl":"https://doi.org/10.1145/2370816.2370908","url":null,"abstract":"Thread Level Speculation (TLS) speculatively executes parts of a program in parallel. Statically determined may dependences between store-load pairs prevent the compiler from speculatively executing parts of programs (e.g loop iterations or functions). If a compiler can determine that the probability of a may dependence occurring at runtime is low, then it can use TLS to execute the loop in parallel. This research will develop a may dependence profiling framework that is able to capture the effect of different inputs on the dependence behaviour of the program during runtime, using a technique called Combined Profiling (CP) [1]. The dependence profiling will be made efficient using the output from static analysis. TLS code generation strategies will be implemented in a version of the LLVM compiler that will generate code for the hardware support for TLS in the IBM BlueGene/Q (BG/Q) machine.","PeriodicalId":403855,"journal":{"name":"2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132613858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
MaSiF: Machine learning guided auto-tuning of Parallel Skeletons MaSiF:机器学习引导的并行骨架自动调优
2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370884
Alexander Collins, Christian Fensch, Hugh Leather
{"title":"MaSiF: Machine learning guided auto-tuning of Parallel Skeletons","authors":"Alexander Collins, Christian Fensch, Hugh Leather","doi":"10.1145/2370816.2370884","DOIUrl":"https://doi.org/10.1145/2370816.2370884","url":null,"abstract":"We present MaSiF, a novel tool to auto-tune parallelization parameters of skeleton parallel programs. It reduces the cost of searching the optimization space using a combination of machine learning and linear dimensionality reduction. To auto-tune a new program, a set of program features is determined statically and used to compute k nearest neighbors from a set of training programs. Previously collected performance data for the nearest neighbors is used to reduce the size of the search space using Principal Components Analysis. This results in a set of eigenvectors that are used to search the reduced space. MaSiF achieves 88% of the performance of the oracle, which searches a random set of 10,000 parameter values. MaSiF searches just 45 points, or 0.45% of the optimization space, to achieve this performance. MaSiF provides an average speedup of 1.18x over parallelization parameters chosen by a human expert.","PeriodicalId":403855,"journal":{"name":"2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT)","volume":"74 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128041923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Hardware prefetchers for emerging parallel applications 用于新兴并行应用程序的硬件预取器
2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370909
Biswabandan Panda, S. Balachandran
{"title":"Hardware prefetchers for emerging parallel applications","authors":"Biswabandan Panda, S. Balachandran","doi":"10.1145/2370816.2370909","DOIUrl":"https://doi.org/10.1145/2370816.2370909","url":null,"abstract":"Hardware prefetching has been studied in the past for multiprogrammed workloads as well as GPUs. Efficient hardware prefetchers like stream-based or GHB-based ones work well for multiprogrammed workloads because different programs get mapped to different cores and are run independently. Parallel applications, however, pose a different set of challenges. Multiple threads of a parallel application share data with each other which brings in coherency issues. Also, local prefetchers do not understand the irregular spread of misses across threads. In this paper, we propose a hardware prefetching framework for L1 D-Cache that targets parallel applications. We show how to make efficient prefetch requests to the L2 cache by studying and classifying the patterns of L1 misses across all the threads. Our preliminary results show an improvement of 7% in execution time on an average on the PARSEC benchmark suite.","PeriodicalId":403855,"journal":{"name":"2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128000301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Layout-oblivious optimization for matrix computations 矩阵计算的布局无关优化
2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370880
Huimin Cui, Qing Yi, Jingling Xue, Xiaobing Feng
{"title":"Layout-oblivious optimization for matrix computations","authors":"Huimin Cui, Qing Yi, Jingling Xue, Xiaobing Feng","doi":"10.1145/2370816.2370880","DOIUrl":"https://doi.org/10.1145/2370816.2370880","url":null,"abstract":"Most scientific computations serve to apply mathematical operations to a set of preconceived data structures, e.g., matrices, vectors, and grids. In this paper, we use a number of widely used matrix computations from the LINPACK library to demonstrate that complex internal organizations of data structures can severely degrade the effectiveness of compilers optimizations. We then present a data layout oblivious optimization methodology, where by isolating an abstract representation of computations from complex implementation details of their data, we enable these computations to be much more accurately analyzed and optimized through varying state-of-the-art compiler technologies.","PeriodicalId":403855,"journal":{"name":"2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127117750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Enhancing performance optimization of multicore chips and multichip nodes with data structure metrics 利用数据结构指标增强多核芯片和多芯片节点的性能优化
2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370838
A. Rane, J. Browne
{"title":"Enhancing performance optimization of multicore chips and multichip nodes with data structure metrics","authors":"A. Rane, J. Browne","doi":"10.1145/2370816.2370838","DOIUrl":"https://doi.org/10.1145/2370816.2370838","url":null,"abstract":"Program performance optimization is usually based solely on measurements of execution behavior of code segments using hardware performance counters. However, memory access patterns are critical performance limiting factors for today's multicore chips where performance is highly memory bound. Therefore diagnoses and selection of optimizations based only on measurements of the execution behavior of code segments are incomplete because they do not incorporate knowledge of memory access patterns and behaviors. This paper presents a low-overhead tool (MACPO) that captures memory traces and computes metrics for the memory access behavior of source-level (C, C++, Fortran) data structures. It also presents a complete process for integrating code segment-based and memory access pattern measurements and analyses for performance optimization specifically targeting multicore chips and multichip nodes of clusters. MACPO explicitly targets the measurement and metrics important to performance optimization for multicore chips. MACPO uses more realistic cache models for computation of latency metrics than those used by previous tools. Evaluation of the effectiveness of adding memory access behavior characteristics of data structures to performance optimization was done on subsets of the ASCI, NAS and Rodina parallel benchmarks and one application program from a domain not represented in these benchmarks. Adding memory behavior characteristics enabled easier diagnoses of bottlenecks and more accurate selection of appropriate optimizations than with only code centric behavior measurements. The performance gains ranged from a few percent to 38 percent.","PeriodicalId":403855,"journal":{"name":"2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122620035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Mileage-based Contention Management in Transactional Memory 事务性内存中基于里程的争用管理
2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370902
Woojin Choi, Lihang Zhao, J. Draper
{"title":"Mileage-based Contention Management in Transactional Memory","authors":"Woojin Choi, Lihang Zhao, J. Draper","doi":"10.1145/2370816.2370902","DOIUrl":"https://doi.org/10.1145/2370816.2370902","url":null,"abstract":"In Transactional Memory (TM), a conflict occurs when a memory block is accessed concurrently by two or more transactions and at least one of them is a write access. The management of conflicts significantly impacts TM performance. There are two alternative approaches for managing conflicts: Reactive Contention Management (RCM) [1] and Proactive Contention Management (PCM) [2]. Previous contention management schemes treat all transactions with no weights, and make a decision based on the information provided by the running transaction instance.","PeriodicalId":403855,"journal":{"name":"2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123912657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Supporting stateful tasks in a dataflow graph 支持数据流图中的有状态任务
2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT) Pub Date : 2012-09-19 DOI: 10.1145/2370816.2370883
Vladimir Gajinov, Srdjan Stipic, O. Unsal, T. Harris, E. Ayguadé, A. Cristal
{"title":"Supporting stateful tasks in a dataflow graph","authors":"Vladimir Gajinov, Srdjan Stipic, O. Unsal, T. Harris, E. Ayguadé, A. Cristal","doi":"10.1145/2370816.2370883","DOIUrl":"https://doi.org/10.1145/2370816.2370883","url":null,"abstract":"This paper introduces Atomic Dataflow Model (ADF) - a programming model for shared-memory systems that combines aspects of dataflow programming with the use of explicitly mutable state. The model provides language constructs that allow a programmer to delineate a program into a set of tasks and to explicitly define input data for each task. This information is conveyed to the ADF runtime system which constructs the task dependency graph and builds the necessary infrastructure for dataflow execution. However, the key aspect of the proposed model is that it does not require the programmer to specify all of the task's dependencies explicitly, but only those that imply logical ordering between tasks. The ADF model manages the remainder of inter-task dependencies automatically, by executing the body of the task within an implicit memory transaction. This provides an easy-to-program optimistic concurrency substrate and enables a task to safely share data with other concurrent tasks. In this paper, we describe the ADF model and show how it can increase the programmability of shared memory systems.","PeriodicalId":403855,"journal":{"name":"2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127704728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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