{"title":"Provably correct posit arithmetic with fixed-point big integer","authors":"S. Chung","doi":"10.1145/3190339.3190341","DOIUrl":"https://doi.org/10.1145/3190339.3190341","url":null,"abstract":"Floating-point number format is used extensively in many applications, especially scientific software. The applications rely on efficient hardware floating-point support to perform arithmetic operations. With the advent of multicore CPUs and massively parallel GPUs, the memory bandwidth of a computer system is increasingly limited for each of the compute cores. The limited memory bandwidth is a serious bottleneck to the system performance. The posit number format [12] is a promising approach to improve the accuracy of the arithmetic operations with more efficient use of bit storage, hence, reducing memory contention. However, robust and reliable software implementations of posit arithmetic libraries in C/C++ or Python are not readily available. In this paper, we seek to develop provably correct posit arithmetic based on fixed-point big integers. A robust and reliable implementation can then serve as a reference for other hardware-optimized implementations, as a test bed for applications to experiment with different posit bit configurations, and to analyze the relative errors of using smaller bit sizes in the posit numbers compared to using the native 32-bit or 64-bit floating-point numbers.","PeriodicalId":402566,"journal":{"name":"Proceedings of the Conference for Next Generation Arithmetic","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125314739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Zoltan Lehoczky, A. Retzler, Richard Toth, Álmos Szabó, Ben Farkas, Krisztian Somogyi
{"title":"High-level .NET software implementations of unum type I and posit with simultaneous FPGA implementation using Hastlayer","authors":"Zoltan Lehoczky, A. Retzler, Richard Toth, Álmos Szabó, Ben Farkas, Krisztian Somogyi","doi":"10.1145/3190339.3190343","DOIUrl":"https://doi.org/10.1145/3190339.3190343","url":null,"abstract":"The unum arithmetic framework has been proposed by Gustafson, D. J. to address the short-comings of the IEEE 754 Standard's floating-point. In this paper, we present our software and hardware implementations of Type I and posit unums. The software implementation is built on the .NET platform as an open source library written in the C# programming language. We automatically create hardware implementations using our .NET to FPGA converter tool called Hastlayer. The amount of hardware resources needed for addition operations are quantified, and the performance of software and prototype hardware for posits are compared. We show that posits are significantly more hardware friendly than Type I unums. Furthermore, our posit FPGA implementation is about 2.04 times more efficient per clock cycle than its software implementation.","PeriodicalId":402566,"journal":{"name":"Proceedings of the Conference for Next Generation Arithmetic","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131859610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The slide number format","authors":"Ignaz Kohlbecker","doi":"10.1145/3190339.3190342","DOIUrl":"https://doi.org/10.1145/3190339.3190342","url":null,"abstract":"The Slide number format divides the real number line into connected sets. Compared to the unum format [3], there is no ubit, no infinity, and values are placed on a logarithmic scale with base 10. Formal definitions for Slides and intervals composed of Slide pairs are provided. The relative error is compared with that of single precision floats. The performance of conversions to and from human readable form is measured.","PeriodicalId":402566,"journal":{"name":"Proceedings of the Conference for Next Generation Arithmetic","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130250720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A matrix-multiply unit for posits in reconfigurable logic leveraging (open)CAPI","authors":"Jianyu Chen, Z. Al-Ars, H. P. Hofstee","doi":"10.1145/3190339.3190340","DOIUrl":"https://doi.org/10.1145/3190339.3190340","url":null,"abstract":"In this paper, we present the design in reconfigurable logic of a matrix multiplier for matrices of 32-bit posit numbers with es=2 [1]. Vector dot products are computed without intermediate rounding as suggested by the proposed posit standard to maximally retain precision. An initial implementation targets the CAPI 1.0 interface on the POWER8 processor and achieves about 10Gpops (Giga posit operations per second). Follow-on implementations targeting CAPI 2.0 and OpenCAPI 3.0 on POWER9 are expected to achieve up to 64Gpops. Our design is available under a permissive open source license at https://github.com/ChenJianyunp/Unum_matrix_multiplier. We hope the current work, which works on CAPI 1.0, along with future community contributions, will help enable a more extensive exploration of this proposed new format.","PeriodicalId":402566,"journal":{"name":"Proceedings of the Conference for Next Generation Arithmetic","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128709966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Universal coding of the reals: alternatives to IEEE floating point","authors":"Peter Lindstrom, Scott Lloyd, J. Hittinger","doi":"10.1145/3190339.3190344","DOIUrl":"https://doi.org/10.1145/3190339.3190344","url":null,"abstract":"We propose a modular framework for representing the real numbers that generalizes ieee, posits, and related floating-point number systems, and which has its roots in universal codes for the positive integers such as the Elias codes. This framework unifies several known but seemingly unrelated representations within a single schema while also introducing new representations. We particularly focus on variable-length encoding of the binary exponent and on the manner in which fraction bits are mapped to values. Our framework builds upon and shares many of the attractive properties of posits but allows for independent experimentation with exponent codes, fraction mappings, reciprocal closure, rounding modes, handling of under- and overflow, and underlying precision.","PeriodicalId":402566,"journal":{"name":"Proceedings of the Conference for Next Generation Arithmetic","volume":"16 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114100107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Proceedings of the Conference for Next Generation Arithmetic","authors":"","doi":"10.1145/3190339","DOIUrl":"https://doi.org/10.1145/3190339","url":null,"abstract":"","PeriodicalId":402566,"journal":{"name":"Proceedings of the Conference for Next Generation Arithmetic","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127459174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}