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Proceedings of the 2014 Forum on Specification and Design Languages (FDL)最新文献

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SystemC AMS power electronic modeling with ideal instantaneous switches SystemC AMS电力电子建模具有理想的瞬时开关
Proceedings of the 2014 Forum on Specification and Design Languages (FDL) Pub Date : 2014-10-01 DOI: 10.1109/FDL.2014.7119365
L. Gil, M. Radetzki
{"title":"SystemC AMS power electronic modeling with ideal instantaneous switches","authors":"L. Gil, M. Radetzki","doi":"10.1109/FDL.2014.7119365","DOIUrl":"https://doi.org/10.1109/FDL.2014.7119365","url":null,"abstract":"Ideal instantaneous switches are a useful behavior abstraction technique to model semiconductor components in power system development. It allows fast and robust simulations of sophisticated power controls. In this paper we present a SystemC AMS extension to support modeling and simulation of externally as well as internally controlled electrical linear networks with ideal switches. By using this model of computation, analog parts composed of large power electronic circuits can be integrated into system level models for design and verification purposes. To validate our implementation, a complex high voltage power converter for medical applications was modeled and simulated. The obtained results demonstrate the robustness and accuracy of this methodology.","PeriodicalId":402037,"journal":{"name":"Proceedings of the 2014 Forum on Specification and Design Languages (FDL)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115133253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Automatic refinement checking for formal system models 正式系统模型的自动精化检查
Proceedings of the 2014 Forum on Specification and Design Languages (FDL) Pub Date : 2014-10-01 DOI: 10.1109/FDL.2014.7119339
J. Seiter, R. Wille, U. Kühne, R. Drechsler
{"title":"Automatic refinement checking for formal system models","authors":"J. Seiter, R. Wille, U. Kühne, R. Drechsler","doi":"10.1109/FDL.2014.7119339","DOIUrl":"https://doi.org/10.1109/FDL.2014.7119339","url":null,"abstract":"For the design of complex systems, formal modeling languages such as UML or SysML find significant attention. The typical model-driven design flow assumes thereby an initial (abstract) model which is iteratively refined to a more precise description. During this process, new errors and inconsistencies might be introduced. In this paper, we propose an automatic method for verifying the consistency of refinements in UML or SysML. For this purpose, a theoretical foundation is considered from which the corresponding proof obligations are determined. Afterwards, they are encoded as an instance of Satisfiability Modulo Theories (SMT) and solved using proper solving engines. The practical use of the proposed method is demonstrated and compared to a previously proposed approach.","PeriodicalId":402037,"journal":{"name":"Proceedings of the 2014 Forum on Specification and Design Languages (FDL)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122089706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A novel modeling framework for time-triggered safety-critical embedded systems 时间触发安全关键型嵌入式系统的新型建模框架
Proceedings of the 2014 Forum on Specification and Design Languages (FDL) Pub Date : 2014-10-01 DOI: 10.1109/FDL.2014.7119343
Iban Ayestaran, C. F. Nicolás, Jon Perez, Asier Larrucea, P. Puschner
{"title":"A novel modeling framework for time-triggered safety-critical embedded systems","authors":"Iban Ayestaran, C. F. Nicolás, Jon Perez, Asier Larrucea, P. Puschner","doi":"10.1109/FDL.2014.7119343","DOIUrl":"https://doi.org/10.1109/FDL.2014.7119343","url":null,"abstract":"This paper presents the Platform Specific Time Triggered Model (PS-TTM), a SystemC based modeling and simulation framework for time-triggered safety-critical embedded systems. The approach facilitates the modeling of Time-Triggered Architecture (TTA) based embedded systems, following a strict separation between the designs of functionality and platform. The PS-TTM provides a value and time domain deterministic simulation environment for an early functional and temporal assessment of the systems. Moreover, the framework includes a time-triggered automatic test executor that enables to perform non-intrusive simulated fault injection (SFI) to the models. The SFI makes an early dependability assessment possible, what reduces the risk of late and expensive discovery of safety related pitfalls. The feasibility of the proposed framework is illustrated with a case study, based on the modeling, simulation and validation of a simplified railway on-board signaling system.","PeriodicalId":402037,"journal":{"name":"Proceedings of the 2014 Forum on Specification and Design Languages (FDL)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128422562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Hybrid dynamic data race detection in systemC systemC中的混合动态数据争用检测
Proceedings of the 2014 Forum on Specification and Design Languages (FDL) Pub Date : 2014-10-01 DOI: 10.1109/FDL.2014.7119347
A. Sen, Onder Kalaci
{"title":"Hybrid dynamic data race detection in systemC","authors":"A. Sen, Onder Kalaci","doi":"10.1109/FDL.2014.7119347","DOIUrl":"https://doi.org/10.1109/FDL.2014.7119347","url":null,"abstract":"Data races are one of the most common problems in concurrent programs. As SystemC standard allows nondeterministic scheduling of processes, this leads to data races. Hence, different executions of the same concurrent program may lead to unexpected results due to race conditions. We develop a hybrid dynamic data race detection algorithm for SystemC/TLM designs that adopts the well-studied dynamic race detection algorithms; lockset and happens-before. Experiments show that our solution has fewer false positives than lockset and fewer false negatives than happens-before algorithms. Our implementation uses dynamic binary instrumentation allowing us to work on designs for which source codes may not be available such as pre-compiled IPs.","PeriodicalId":402037,"journal":{"name":"Proceedings of the 2014 Forum on Specification and Design Languages (FDL)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114403619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Synthesizing code for GPGPUs from abstract formal models 从抽象形式模型合成gpgpu代码
Proceedings of the 2014 Forum on Specification and Design Languages (FDL) Pub Date : 2014-10-01 DOI: 10.1109/FDL.2014.7119363
Gabriel Hjort Blindell, Christian Menne, I. Sander
{"title":"Synthesizing code for GPGPUs from abstract formal models","authors":"Gabriel Hjort Blindell, Christian Menne, I. Sander","doi":"10.1109/FDL.2014.7119363","DOIUrl":"https://doi.org/10.1109/FDL.2014.7119363","url":null,"abstract":"Today multiple frameworks exist for elevating the task of writing programs for GPGPUs, which are massively dataparallel execution platforms. These are needed as writing correct and high-performing applications for GPGPUs is notoriously difficult due to the intricacies of the underlying architecture. However, the existing frameworks lack a formal foundation that makes them difficult to use together with formal verification, testing, and design space exploration. We present in this paper a novel software synthesis tool - called f2cc - which is capable of generating efficient GPGPU code from abstract formal models based on the synchronous model of computation. These models can be built using high-level modeling methodologies that hide low-level architecture details from the developer. The correctness of the tool has been experimentally validated on models derived from two applications. The experiments also demonstrate that the synthesized GPGPU code yielded a 28 x speedup when executed on a graphics card with 96 cores and compared against a sequential version that uses only the CPU.","PeriodicalId":402037,"journal":{"name":"Proceedings of the 2014 Forum on Specification and Design Languages (FDL)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129537700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Dependable task and communication migration in tiled manycore system-on-chip 平铺多核片上系统的可靠任务和通信迁移
Proceedings of the 2014 Forum on Specification and Design Languages (FDL) Pub Date : 2014-10-01 DOI: 10.1109/FDL.2014.7119361
Stefan Wallentowitz, S. Rosch, Thomas Wild, A. Herkersdorf, Volker Wenzel, J. Henkel
{"title":"Dependable task and communication migration in tiled manycore system-on-chip","authors":"Stefan Wallentowitz, S. Rosch, Thomas Wild, A. Herkersdorf, Volker Wenzel, J. Henkel","doi":"10.1109/FDL.2014.7119361","DOIUrl":"https://doi.org/10.1109/FDL.2014.7119361","url":null,"abstract":"Power densities and thermal hotspots are a major concern for the dependability of future multi-processor systemon- chip. They can lead to transient faults affecting the functionality in the short term and can cause permanent damage of a device. The dependability problem can be tackled on different layers such as technology hardening or application awareness. This work is based on an approach that addresses the issue for tile-based manycore system-on-chip on software and architecture layer. An agent-based system management employs task migration to react to thermal hotspots and pro-actively avoid them. The inter-task communication plays an important role as communication channels need to be migrated accordingly. The presented work focuses on the issue of communication migration and is based on the idea of handling it transparently to the task migration. Network-on-chip protection switching techniques have been introduced before and in this paper we evaluate the potential and bottlenecks of such methods in a realistic platform.","PeriodicalId":402037,"journal":{"name":"Proceedings of the 2014 Forum on Specification and Design Languages (FDL)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128391224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Automating the translation of assertions using natural language processing techniques 使用自然语言处理技术自动翻译断言
Proceedings of the 2014 Forum on Specification and Design Languages (FDL) Pub Date : 2014-10-01 DOI: 10.1109/FDL.2014.7119356
Mathias Soeken, Christopher B. Harris, Nabila Abdessaied, I. Harris, R. Drechsler
{"title":"Automating the translation of assertions using natural language processing techniques","authors":"Mathias Soeken, Christopher B. Harris, Nabila Abdessaied, I. Harris, R. Drechsler","doi":"10.1109/FDL.2014.7119356","DOIUrl":"https://doi.org/10.1109/FDL.2014.7119356","url":null,"abstract":"In order to verify natural language assertions from a specification automatically, they need to be translated into formal representations. This process is error-prone and can lead to a product that does not meet the initial intentions.We automate this process by first partitioning all assertions into subsets based on sentence similarity and then providing a translation template for each subset which must be completed by the designer. Since many assertions are described by similar sentences, the number of manual translation steps can be decreased significantly. We evaluated our approach by translating English constraint sentences from an industrial specification into SystemVerilog assertions.","PeriodicalId":402037,"journal":{"name":"Proceedings of the 2014 Forum on Specification and Design Languages (FDL)","volume":"978-2-9530504-9-3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128675731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Verifying consistency between activity diagrams and their corresponding OCL contracts 验证活动图及其相应的OCL契约之间的一致性
Proceedings of the 2014 Forum on Specification and Design Languages (FDL) Pub Date : 2014-10-01 DOI: 10.1109/FDL.2014.7119340
Christoph Hilken, J. Seiter, R. Wille, U. Kühne, R. Drechsler
{"title":"Verifying consistency between activity diagrams and their corresponding OCL contracts","authors":"Christoph Hilken, J. Seiter, R. Wille, U. Kühne, R. Drechsler","doi":"10.1109/FDL.2014.7119340","DOIUrl":"https://doi.org/10.1109/FDL.2014.7119340","url":null,"abstract":"Modeling languages such as SysML provide various description means for a precise specification of the desired system. As a system model typically uses multiple diagram types focusing on different aspects, it is crucial to keep them consistent to each other. In this paper, we propose a verification methodology which ensures the consistency between activity diagrams as blueprints for the implementation and their contracts from a block definition diagram. For this purpose, activity diagrams are transformed to OCL constraints that can be checked against pre- and postconditions. The proposed approach is evaluated in a case study based on an industrial specification.","PeriodicalId":402037,"journal":{"name":"Proceedings of the 2014 Forum on Specification and Design Languages (FDL)","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128131895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Multi-level modeling of wireless embedded systems 无线嵌入式系统的多级建模
Proceedings of the 2014 Forum on Specification and Design Languages (FDL) Pub Date : 2014-10-01 DOI: 10.1109/FDL.2014.7119349
Fangyan Li, E. Dekneuvel, G. Jacquemod, D. Quaglia, M. Lora, F. Pêcheux, Remi Butaud
{"title":"Multi-level modeling of wireless embedded systems","authors":"Fangyan Li, E. Dekneuvel, G. Jacquemod, D. Quaglia, M. Lora, F. Pêcheux, Remi Butaud","doi":"10.1109/FDL.2014.7119349","DOIUrl":"https://doi.org/10.1109/FDL.2014.7119349","url":null,"abstract":"The design of wireless embedded systems needs their efficient and realistic simulation to verify that requirements are met. The reproduction of communication behavior is crucial to assess the performance of hardware and software components, e.g., dependability and energy consumption. This work presents and discusses different levels of abstraction for the simulation of the communication behavior. Each level addresses different aspects of the communication and allows to specify different kinds of detail; furthermore, it requires a specific modeling approach. Their use and the corresponding computational overhead is shown in the specific case of the Bluetooth standard. We also show that simulation results obtained at a low abstraction level can be used at a higher one to drive design choices.","PeriodicalId":402037,"journal":{"name":"Proceedings of the 2014 Forum on Specification and Design Languages (FDL)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132695982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A concept for design of embedded systems at semantic level 语义级嵌入式系统设计的概念
Proceedings of the 2014 Forum on Specification and Design Languages (FDL) Pub Date : 2014-10-01 DOI: 10.1109/FDL.2014.7119352
Frank Wawrzik, Javier Moreno Molina, C. Grimm
{"title":"A concept for design of embedded systems at semantic level","authors":"Frank Wawrzik, Javier Moreno Molina, C. Grimm","doi":"10.1109/FDL.2014.7119352","DOIUrl":"https://doi.org/10.1109/FDL.2014.7119352","url":null,"abstract":"The paper proposes a concept that aims at putting the design of embedded systems at a new, higher level of abstraction. Until now, there is a gap of several weeks of modeling efforts between an initial block diagram sketched on a blackboard and first executable models for e.g. architecture exploration and virtual prototyping. Being able to simulate during or short after initial discussions would be of great benefit. The idea is to provide a library of \"smart\" models that fill missing details by context knowledge represented in ontologies. In particular, communication between software and peripheral units is replaced by (semantic) references to ontologies. The library is partially implemented based on SystemC (TLM, AMS) and work in progress. For demonstration, a model of an electronic throttle control is modeled at semantic level.","PeriodicalId":402037,"journal":{"name":"Proceedings of the 2014 Forum on Specification and Design Languages (FDL)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126431846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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