2014 International Symposium on System-on-Chip (SoC)最新文献

I/O virtualization utilizing an efficient hardware system-level Memory Management Unit I/O虚拟化利用一个高效的硬件系统级内存管理单元

2014 International Symposium on System-on-Chip (SoC) Pub Date : 2014-12-04 DOI: 10.1109/ISSOC.2014.6972448

Georgios Kornaros, K. Harteros, I. Christoforakis, M. Astrinaki

引用次数: 15

Early power-aware Design Space Exploration for embedded systems: MPEG-2 case study 嵌入式系统的早期功耗感知设计空间探索:MPEG-2案例研究

2014 International Symposium on System-on-Chip (SoC) Pub Date : 2014-12-04 DOI: 10.1109/ISSOC.2014.6972450

Feriel Ben Abdallah, C. Trabelsi, R. B. Atitallah, M. Abed

{"title":"Early power-aware Design Space Exploration for embedded systems: MPEG-2 case study","authors":"Feriel Ben Abdallah, C. Trabelsi, R. B. Atitallah, M. Abed","doi":"10.1109/ISSOC.2014.6972450","DOIUrl":"https://doi.org/10.1109/ISSOC.2014.6972450","url":null,"abstract":"Power consumption has become one of the major concerns in embedded systems design, especially for mobile devices, which integrate many applications leading to a high power consumption. In this context, designers have the challenge to identify power issues early in the design flow and to explore the largest possible space of power-efficient solutions. In this paper, we present a Model Driven Engineering (MDE) approach for early power-aware Design Space Exploration (DSE). This approach is based on a high-level modeling of power estimation and dynamic management aspects targeting an automatic generation of the corresponding simulation code. It was implemented in the DSE toolkit TTool by integrating power concepts in its DIPLODOCUS UML profile. The existing C++ simulation code generator was extended in order to integrate power estimation. The main objective of this article is to illustrate the potential of our approach through an MPEG-2 case study. The proposed high-level power modeling concepts were used to target two different platforms for the implementation of an MPEG-2 decoding application. The processor power estimates obtained from simulations were compared to real board measurements. This comparison showed that our MDE approach is capable of obtaining results that can be used to make early power-efficient design decisions.","PeriodicalId":401348,"journal":{"name":"2014 International Symposium on System-on-Chip (SoC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115178584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

System on chip design of a linear system solver 一个线性系统求解器的片上系统设计

2014 International Symposium on System-on-Chip (SoC) Pub Date : 2014-12-04 DOI: 10.1109/ISSOC.2014.6972445

J. Bucek, P. Kubalík, R. Lórencz, T. Zahradnický

引用次数: 6

A communication model and partitioning algorithm for streaming applications for an embedded MPSoC 一种嵌入式MPSoC流应用的通信模型和分区算法

2014 International Symposium on System-on-Chip (SoC) Pub Date : 2014-12-04 DOI: 10.1109/ISSOC.2014.6972436

W. Kelly, Martin Flasskamp, Gregor Sievers, J. Ax, Jianing Chen, Christian Klarhorst, Christoph Ragg, T. Jungeblut, Andrew Sorensen

引用次数: 17

Implementation of Multicore communications API 多核通信API的实现

2014 International Symposium on System-on-Chip (SoC) Pub Date : 2014-12-04 DOI: 10.1109/ISSOC.2014.6972434

Janne Virtanen, Lauri Matilainen, E. Salminen, T. Hämäläinen

{"title":"Implementation of Multicore communications API","authors":"Janne Virtanen, Lauri Matilainen, E. Salminen, T. Hämäläinen","doi":"10.1109/ISSOC.2014.6972434","DOIUrl":"https://doi.org/10.1109/ISSOC.2014.6972434","url":null,"abstract":"This paper presents an implementation of Multicore Communications API (MCAPI), with focus on portability, stability, and simplicity of the design. The main motivation for the implementation is instability of other publicly available implementations. The developed implementation utilizes POSIX message queues, that is an easily portable interface and readily compatible with MCAPI. The performance was measured as latency and transfer rate of the API. The measurement platforms were a x86-64 PC and a development board featuring an ARM processor. A MCAPI implementation was used as reference for comparison. PMQ-MCAPI is much more stable and easily usable than other MCAPI implementations publicly available for PC. When transfer size was between 1-8 KiB, latency of transfers between cores was between 9-15 μs and transfer rate 500-5000 MBps. This translates to 27 000-45 000 cycles and 0.16-1.67 bytes per cycle. CPU and especially performance of its cache were concluded as the most important factors contributing to the performance. In comparison to the reference, latency of the implementation was 1/8 at best, while transfer rate was up to 35x.","PeriodicalId":401348,"journal":{"name":"2014 International Symposium on System-on-Chip (SoC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116008118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Energy-efficiency of floating-point and fixed-point SIMD cores for MIMO processing systems MIMO处理系统中浮点和定点SIMD核的能源效率

2014 International Symposium on System-on-Chip (SoC) Pub Date : 2014-12-04 DOI: 10.1109/ISSOC.2014.6972429

D. Günther, Andreas Bytyn, R. Leupers, G. Ascheid

{"title":"Energy-efficiency of floating-point and fixed-point SIMD cores for MIMO processing systems","authors":"D. Günther, Andreas Bytyn, R. Leupers, G. Ascheid","doi":"10.1109/ISSOC.2014.6972429","DOIUrl":"https://doi.org/10.1109/ISSOC.2014.6972429","url":null,"abstract":"For computational tasks with regular data access patterns, e.g. vector arithmetic, single instruction multiple data (SIMD) processor cores present a viable alternative to application-specific integrated circuits (ASICs). Even though the additional flexibility of a programmable core comes at the expense of reduced area- and energy efficiency, this price is potentially worth paying in application domains with a multitude of standards and use cases as it is the case in the domain of wireless communications. The high dynamic range of values that occurs in multi-antenna wireless baseband processing calls for the use of numerical stabilization measures like QR factorization and scaling when operating on a fixed-point processor core. A floating-point core on the other hand covers a wider dynamic range, rendering such measures unnecessary at the price of increased power consumption. This work compares a floating-point and a fixed-point SIMD core in a case study of linear MIMO detection. After evaluating the numerical precision requirements, the achievable throughput of both cores is compared along with the maximum achievable area- and energy efficiency for several use cases, resulting in an assessment as to which number format is best suited for which use case.","PeriodicalId":401348,"journal":{"name":"2014 International Symposium on System-on-Chip (SoC)","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129896176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Parallel and distributed simulation of networked multi-core systems 网络化多核系统的并行与分布式仿真

2014 International Symposium on System-on-Chip (SoC) Pub Date : 2014-12-04 DOI: 10.1109/ISSOC.2014.6972446

P. Wehner, D. Göhringer

引用次数: 5

Keyed logic BIST for Trojan detection in SoC SoC中木马检测的键控逻辑BIST

2014 International Symposium on System-on-Chip (SoC) Pub Date : 2014-12-04 DOI: 10.1109/ISSOC.2014.6972433

E. Dubrova, M. Näslund, G. Carlsson, B. Smeets

引用次数: 14

A cycle-accurate Network-on-Chip simulator with support for abstract task graph modeling 一个周期精确的片上网络模拟器，支持抽象任务图建模

2014 International Symposium on System-on-Chip (SoC) Pub Date : 2014-12-04 DOI: 10.1109/ISSOC.2014.6972440

J. Joseph, Thilo Pionteck

引用次数: 8

Fast Memory Region: 3D DRAM memory concept evaluated for JPEG2000 algorithm 快速记忆区域:3D DRAM记忆体概念评估JPEG2000演算法

2014 International Symposium on System-on-Chip (SoC) Pub Date : 2014-12-04 DOI: 10.1109/ISSOC.2014.6972443

A. Schönberger, K. Hofmann

引用次数: 1