2006 Formal Methods in Computer Aided Design最新文献

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Formal Analysis and Verification of an OFDM Modem Design using HOL 基于HOL的OFDM调制解调器设计的形式化分析与验证
2006 Formal Methods in Computer Aided Design Pub Date : 2006-11-12 DOI: 10.1109/FMCAD.2006.14
A. M. Abdullah, Behzad Akbarpour, S. Tahar
{"title":"Formal Analysis and Verification of an OFDM Modem Design using HOL","authors":"A. M. Abdullah, Behzad Akbarpour, S. Tahar","doi":"10.1109/FMCAD.2006.14","DOIUrl":"https://doi.org/10.1109/FMCAD.2006.14","url":null,"abstract":"In this paper we formally specify and verify an implementation of the IEEE802.11a standard physical layer based OFDM (orthogonal frequency division multiplexing) modem using the HOL (higher order logic) theorem prover. The versatile expressive power of HOL helped model the original design at all abstraction levels starting from a floating-point model to the fixed-point design and then synthesized and implemented in FPGA technology. The paper also investigates the rounding error accumulated during ideal real to floating-point and fixed-point transitions at the algorithmic level","PeriodicalId":400704,"journal":{"name":"2006 Formal Methods in Computer Aided Design","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131033969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Model Checking Data-Dependent Real-Time Properties of the European Train Control System 欧洲列车控制系统数据相关实时性的模型检验
2006 Formal Methods in Computer Aided Design Pub Date : 2006-11-12 DOI: 10.1109/FMCAD.2006.21
Johannes Faber, R. Meyer
{"title":"Model Checking Data-Dependent Real-Time Properties of the European Train Control System","authors":"Johannes Faber, R. Meyer","doi":"10.1109/FMCAD.2006.21","DOIUrl":"https://doi.org/10.1109/FMCAD.2006.21","url":null,"abstract":"The behavior of embedded hardware and software systems is determined by at least three dimensions: control flow, data aspects, and real-time requirements. To specify the different dimensions of a system with the best-suited techniques, the formal language CSP-OZ-DC (Hoenicke and Maier, 2005) integrates communicating sequential processes (CSP) (Hoare, 1985), Object-Z (OZ) (Smith, 2000), and duration calculus (DC) (Zhou and Hansen, 2004) into a declarative formalism equipped with a unified and compositional semantics. In this paper, we provide evidence that CSP-OZ-DC is a convenient language for modeling systems of industrial relevance. To this end, we examine the emergency message handling in the European train control system (ETCS) as a case study with uninterpreted constants and infinite data domains. We automatically verify that our model ensures real-time safety properties, which crucially depend on the system's data handling. Related work on ETCS case studies focuses on stochastic examinations of the communication reliability (Hermanns et al., 2005; Zimmermann and Hommel, 2005). The components' data aspects are neglected, though","PeriodicalId":400704,"journal":{"name":"2006 Formal Methods in Computer Aided Design","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115433919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
Thorough Checking Revisited 重新进行彻底检查
2006 Formal Methods in Computer Aided Design Pub Date : 2006-11-12 DOI: 10.1109/FMCAD.2006.33
S. Nejati, M. Bobaru, M. Chechik
{"title":"Thorough Checking Revisited","authors":"S. Nejati, M. Bobaru, M. Chechik","doi":"10.1109/FMCAD.2006.33","DOIUrl":"https://doi.org/10.1109/FMCAD.2006.33","url":null,"abstract":"Previous years have seen a proliferation of 3-valued models for capturing abstractions of systems, since these enable verifying both universal and existential properties. Reasoning about such systems is either inexpensive and imprecise (compositional checking), or expensive and precise (thorough checking). In this paper, we prove that thorough and compositional checks for temporal formulas in their disjunctive forms coincide, which leads to an effective procedure for thorough checking of a variety of abstract models and the entire mu-calculus","PeriodicalId":400704,"journal":{"name":"2006 Formal Methods in Computer Aided Design","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117273121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Assume-Guarantee Reasoning for Deadlock 死锁的假设保证推理
2006 Formal Methods in Computer Aided Design Pub Date : 2006-11-12 DOI: 10.1109/FMCAD.2006.8
S. Chaki, Nishant Sinha
{"title":"Assume-Guarantee Reasoning for Deadlock","authors":"S. Chaki, Nishant Sinha","doi":"10.1109/FMCAD.2006.8","DOIUrl":"https://doi.org/10.1109/FMCAD.2006.8","url":null,"abstract":"We extend the learning-based automated assume guarantee paradigm to perform compositional deadlock detection. We define failure automata, a generalization of finite automata that accept regular failure sets. We develop a learning algorithm LF that constructs the minimal deterministic failure automaton accepting any unknown regular failure set using a minimally adequate teacher. We show how LF can be used for compositional regular failure language containment, and deadlock detection, using non-circular and circular assume guarantee rules. We present an implementation of our techniques and encouraging experimental results on several non-trivial benchmarks","PeriodicalId":400704,"journal":{"name":"2006 Formal Methods in Computer Aided Design","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129430052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Automatic Generation of Schedulings for Improving the Test Coverage of Systems-on-a-Chip 提高片上系统测试覆盖率的调度自动生成
2006 Formal Methods in Computer Aided Design Pub Date : 2006-11-12 DOI: 10.1109/FMCAD.2006.10
C. Helmstetter, F. Maraninchi, L. Maillet-Contoz, M. Moy
{"title":"Automatic Generation of Schedulings for Improving the Test Coverage of Systems-on-a-Chip","authors":"C. Helmstetter, F. Maraninchi, L. Maillet-Contoz, M. Moy","doi":"10.1109/FMCAD.2006.10","DOIUrl":"https://doi.org/10.1109/FMCAD.2006.10","url":null,"abstract":"SystemC is becoming a de-facto standard for the early simulation of systems-on-a-chip (SoCs). It is a parallel language with a scheduler. Testing a SoC written in SystemC implies that we execute it, for some well chosen data. We are bound to use a particular deterministic implementation of the scheduler, whose specification is non-deterministic. Consequently, we may fail to discover bugs that would have appeared using another valid implementation of the scheduler. Current methods for testings SoCs concentrate on the generation of the inputs, and do not address this problem at all. We assume that the selection of relevant data is already done, and we generate several schedulings allowed by the scheduler specification. We use dynamic partial-order reduction techniques to avoid the generation of two schedulings that have the same effect on the system's behavior. Exploring alternative schedulings during testing is a way of guaranteeing that the SoC description, and in particular the embedded software, is scheduler-independent, hence more robust. The technique extends to the exploration of other non-fully specified aspects of SoC descriptions, like timing","PeriodicalId":400704,"journal":{"name":"2006 Formal Methods in Computer Aided Design","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128652357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 59
An Integration of HOL and ACL2 HOL和ACL2的集成
2006 Formal Methods in Computer Aided Design Pub Date : 2006-11-12 DOI: 10.1109/FMCAD.2006.6
M. Gordon, James Reynolds, W. Hunt, Matt Kaufmann
{"title":"An Integration of HOL and ACL2","authors":"M. Gordon, James Reynolds, W. Hunt, Matt Kaufmann","doi":"10.1109/FMCAD.2006.6","DOIUrl":"https://doi.org/10.1109/FMCAD.2006.6","url":null,"abstract":"A link between the ACL2 and HOL4 proof assistants is described. This allows each system to be deployed smoothly within a single formal development. Several applications are being considered: using ACL2's execution environment for simulating HOL models; using ACL2's proof automation to discharge HOL proof obligations; and using HOL to specify and verify properties of ACL2 functions that cannot easily be stated in the first-order ACL2 logic. Care has been taken to ensure sound translations between the logics supported by HOL and ACL2. The initial ACL2 theory has been defined inside HOL, so that it is possible to prove mechanically that first-order ACL2 functions on S-expressions correspond to higher-order functions operating on a variety of types. The translation between the two systems operates at the level of S-expressions and is intended to handle large hardware and software models","PeriodicalId":400704,"journal":{"name":"2006 Formal Methods in Computer Aided Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129221274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
An Improved Distance Heuristic Function for Directed Software Model Checking 一种用于有向软件模型检验的改进距离启发式函数
2006 Formal Methods in Computer Aided Design Pub Date : 2006-11-12 DOI: 10.1109/FMCAD.2006.5
Neha Rungta, Eric Mercer
{"title":"An Improved Distance Heuristic Function for Directed Software Model Checking","authors":"Neha Rungta, Eric Mercer","doi":"10.1109/FMCAD.2006.5","DOIUrl":"https://doi.org/10.1109/FMCAD.2006.5","url":null,"abstract":"State exploration in directed software model checking is guided using a heuristic function to move states near errors to the front of the search queue. Distance heuristic functions rank states based on the number of transitions needed to move the current program state into an error location. Lack of calling context information causes the heuristic function to underestimate the true distance to the error; however, inlining functions at call sites in the control flow graph to capture calling context leads to an exponential growth in the computation. This paper presents a new algorithm that implicitly inlines functions at call sites to compute distance data with unbounded calling context that is polynomial in the number of nodes in the control flow graph. The new algorithm propagates distance data through call sites during a depth-first traversal of the program. We show in a series of benchmark examples that the new heuristic function with unbounded distance data is more efficient than the same heuristic function that inlines functions at their call sites up to a certain depth","PeriodicalId":400704,"journal":{"name":"2006 Formal Methods in Computer Aided Design","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122952153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Symmetry Reduction for STE Model Checking STE模型检验的对称性约简
2006 Formal Methods in Computer Aided Design Pub Date : 2006-11-12 DOI: 10.1109/FMCAD.2006.31
A. Darbari
{"title":"Symmetry Reduction for STE Model Checking","authors":"A. Darbari","doi":"10.1109/FMCAD.2006.31","DOIUrl":"https://doi.org/10.1109/FMCAD.2006.31","url":null,"abstract":"In spite of the tremendous success of STE model checking one cannot verify circuits with arbitrary large number of state holding elements. In this paper we present a methodology of symmetry reduction for STE model checking, using a novel set of STE inference rules. For symmetric circuit models these rules provide a very effective reduction strategy. When used as tactics, rules help decompose a given STE property to a set containing several classes of equivalent STE properties. A representative from each equivalence class is picked and verified using an STE simulator, and the correctness of the entire class of assertions is deduced, using a theorem that we provide. Finally inference rules are used in the forward direction to deduce the overall statement of correctness. Our experiments on verifying arbitrarily large CAMs and circuits with multiple CAMs, show that these can be verified using a fixed, small number of BDD variables","PeriodicalId":400704,"journal":{"name":"2006 Formal Methods in Computer Aided Design","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116723258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Simulation Bounds for Equivalence Verification of Arithmetic Datapaths with Finite Word-Length Operands 有限字长操作数算术数据路径等价性验证的模拟边界
2006 Formal Methods in Computer Aided Design Pub Date : 2006-11-12 DOI: 10.1109/FMCAD.2006.30
N. Shekhar, P. Kalla, Brandon Meredith, Florian Enescu
{"title":"Simulation Bounds for Equivalence Verification of Arithmetic Datapaths with Finite Word-Length Operands","authors":"N. Shekhar, P. Kalla, Brandon Meredith, Florian Enescu","doi":"10.1109/FMCAD.2006.30","DOIUrl":"https://doi.org/10.1109/FMCAD.2006.30","url":null,"abstract":"This paper addresses simulation-based verification of high-level descriptions of arithmetic datapaths. Instances of such designs are commonly found in DSP for audio, video and multimedia applications, where the word-lengths of input/output bit-vectors are fixed according to the desired precision. Initial descriptions of such systems are usually specified as Matlab/C code. These are then automatically translated into behavioural/RTL descriptions (HDL) for subsequent hardware synthesis. In order to verify that the initial Matlab/C model is bit-true equivalent to the translated RTL, how many simulation vectors need to be applied? This paper explores results from number theory and commutative algebra to show that exhaustive simulation is not necessary for testing their equivalence. In particular, we derive an upper bound on the number of simulation vectors required to prove equivalence or identify bugs. These vectors cannot be arbitrarily generated; we determine exactly those vectors that need to be simulated. Extensive experiments are performed within practical CAD settings to demonstrate the validity and applicability of these results","PeriodicalId":400704,"journal":{"name":"2006 Formal Methods in Computer Aided Design","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133335190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Advanced Unbounded Model Checking Based on AIGs, BDD Sweeping, And Quantifier Scheduling 基于AIGs、BDD扫描和量词调度的高级无界模型检查
2006 Formal Methods in Computer Aided Design Pub Date : 2006-11-12 DOI: 10.1109/FMCAD.2006.4
Florian Pigorsch, Christoph Scholl, Stefan Disch
{"title":"Advanced Unbounded Model Checking Based on AIGs, BDD Sweeping, And Quantifier Scheduling","authors":"Florian Pigorsch, Christoph Scholl, Stefan Disch","doi":"10.1109/FMCAD.2006.4","DOIUrl":"https://doi.org/10.1109/FMCAD.2006.4","url":null,"abstract":"In this paper we present a complete method for verifying properties expressed in the temporal logic CTL. In contrast to the majority of verification methods presented in previous years, we support unbounded model checking based on symbolic representations of characteristic functions. Among others, our method is based on an advanced and-inverter graph (AIG) implementation, quantifier scheduling, and BDD sweeping. For several examples, our method outperforms BDD based symbolic model checking by orders of magnitude. However, our approach is also able to produce competitive results for cases where BDD are known to perform well","PeriodicalId":400704,"journal":{"name":"2006 Formal Methods in Computer Aided Design","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122977038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
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