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Behavioral Synthesis for Hardware Security最新文献

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State Encoding Based Watermarking of Sequential Circuits Using Hybridized Darwinian Genetic Algorithm 基于状态编码的序列电路的杂交达尔文遗传算法水印
Behavioral Synthesis for Hardware Security Pub Date : 1900-01-01 DOI: 10.1007/978-3-030-78841-4_9
Matthew Lewandowski, S. Katkoori
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引用次数: 0
Behavioral Synthesis for Hardware Security 硬件安全的行为综合
Behavioral Synthesis for Hardware Security Pub Date : 1900-01-01 DOI: 10.1007/978-3-030-78841-4
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引用次数: 1
Generation and Verification of Timing Attack Resilient Schedules During the High-Level Synthesis of Integrated Circuits 集成电路高级合成中时序攻击弹性调度的生成与验证
Behavioral Synthesis for Hardware Security Pub Date : 1900-01-01 DOI: 10.1007/978-3-030-78841-4_15
Steffen Peter, T. Givargis
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引用次数: 1
Encoding of Finite-State Controllers for Graded Security and Power 分级安全与功率有限状态控制器的编码
Behavioral Synthesis for Hardware Security Pub Date : 1900-01-01 DOI: 10.1007/978-3-030-78841-4_8
Richa Agrawal, R. Vemuri
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引用次数: 0
Protecting Hardware IP Cores During High-Level Synthesis 在高级合成过程中保护硬件IP核
Behavioral Synthesis for Hardware Security Pub Date : 1900-01-01 DOI: 10.1007/978-3-030-78841-4_6
C. Pilato, D. Sciuto, F. Regazzoni, S. Garg, R. Karri
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引用次数: 0
S*FSMs for Reduced Information Leakage: Power Side Channel Protection Through Secure Encoding 减少信息泄漏的FSMs:通过安全编码的电源侧通道保护
Behavioral Synthesis for Hardware Security Pub Date : 1900-01-01 DOI: 10.1007/978-3-030-78841-4_14
M. Borowczak, R. Vemuri
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引用次数: 0
Hardware IP Protection Using Register Transfer Level Locking and Obfuscation of Control and Data Flow 使用寄存器传输级锁定和控制流和数据流混淆的硬件IP保护
Behavioral Synthesis for Hardware Security Pub Date : 1900-01-01 DOI: 10.1007/978-3-030-78841-4_4
Pranesh Santikellur, R. Chakraborty, S. Bhunia
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引用次数: 2
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