Memory Technology, Design, and Testing最新文献

{"title":"Panel on Advanced Embedded Memory Technologies","authors":"B. Cockburn","doi":"10.1109/MTDT.2002.1029782","DOIUrl":"https://doi.org/10.1109/MTDT.2002.1029782","url":null,"abstract":"At present, system-on-a-chip (SoC) designers are confronted with a variety of alternative embedded memory technologies including SRAM, DRAM, and flash memory. Each of these memory options has both strengths and weaknesses. SRAM offers compatibility with logic and fast read and write speeds at the cost of large 4- or 6-transistor storage cells and relatively high dynamic power consumption. DRAM offers high storage density, but embedding DRAM in an SoC design typically requires expensive modifications to standard logic processes and usually entails compromises to the performance of the resulting logic and/or memory. Neither SRAM nor DRAM offers nonvolatility, which is essential for some applications and would be attractive for many others. Flash memory and EEPROM macros are both available in standard foundry processes, but the minimum available feature sizes are typically one to two generations behind state-of-the-art line widths. Also, provisions must be made for providing high programming voltages. Several emerging nonvolatile memory technologies are under active development. Some of these are touted as having the potential to become the ultimate memory for SoC designs, combining nonvolatility with access times approaching those of SRAM and densities approaching those of DRAM. Magneto-resistive memory (MRAM) is being developed at Motorola and collaboratively by IBM and Infineon Technologies. Motorola believes that MRAM has the potential to become a \"universal memory\" technology that will have wide application in portable computers, consumer electronics, and wireless devices. Ferroelectric memory (FeRAM and FRAM) is under development by numerous companies, including Ramtron, Fujitsu, Intel, Samsung, and collaboratively by Infineon and Toshiba. FeRAM is also touted as potentially being a universal memory technology for SoCs. A third candidate memory technology, called ovonics unified memory (OUM), is being investigated by STMicroelectronics, British Aerospace, and collaboratively by Intel, Azalea Microelectronics and Ovonyx. Intel believes that OUM may be easier to integrate with standard CMOS than MRAM, but the industry's largest player appears to be backing research drives in both OUM and FeRAM. All three of these nonvolatile technologies show promise for integration in CMOS processes, although it is unclear how soon these technologies will become available at leading edge line widths. The panel will include advocates of MRAM, FeRAM and OUM. The participants will argue the merits of their respective technologies with respect to the alternatives.","PeriodicalId":396830,"journal":{"name":"Memory Technology, Design, and Testing","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131000861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Crosstalk in Deep Submicron DRAMs","authors":"Zemo Yang, S. Mourad","doi":"10.1109/MTDT.2000.868626","DOIUrl":"https://doi.org/10.1109/MTDT.2000.868626","url":null,"abstract":"This study examines the effect of crosstalk on the operations of DRAMs that are implemented in deep submicron technology, 0.18 µm. An extensive simulation revealed that the coupling between word lines and between bit lines alter the cell contents during reading and writing operations as well as retention of the different cells The effect is more likely when the poly instead of aluminum is used. Coupling between bit and word lines did not have such serious outcome.","PeriodicalId":396830,"journal":{"name":"Memory Technology, Design, and Testing","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121655716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low Power SRAMs for Battery Operation","authors":"M. Margala","doi":"10.1109/MTDT.1999.10000","DOIUrl":"https://doi.org/10.1109/MTDT.1999.10000","url":null,"abstract":"In recent years, a growing class of personal computing devices has emerged including portable desktops, digital pens, and new audio- and video-based multimedia products. Other new products include wireless communications and imaging systems such as personal digital assistants, personal communicators and smart cards. These devices and systems demand high-speed, high-throughput computations, complex functionalities and often real-time processing capabilities. A key challenge is that the performance of these devices is limited by the size, weight and lifetime of batteries. Battery-operated applications demand new design approaches and methodologies that produce more power-efficient designs, which means significant reductions in power consumption for the same level of performance. Memories such as static random-access memories (SRAMs) contribute to the total system power consumption by up to 50% [1]. This tutorial presentation focuses on critical concepts and circuit techniques that result in significant savings of active and standby power in SRAMs. The topics covered in this tutorial include the following: a brief overview of SRAM architecture and operation; sources of active and standby power dissipation in SRAMs; capacitance reduction techniques; AC and DC power reduction techniques; pulse operation techniques; operating voltage scaling and low-power sensing; and leakage current suppression.","PeriodicalId":396830,"journal":{"name":"Memory Technology, Design, and Testing","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131766487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}