2009 IEEE International Symposium on Workload Characterization (IISWC)最新文献

Message from the program chair 来自节目主持人的信息

2009 IEEE International Symposium on Workload Characterization (IISWC) Pub Date : 2021-12-01 DOI: 10.1109/DEXA.2006.87

T. Conte

引用次数: 0

Message from the general chair 主席的口信

2009 IEEE International Symposium on Workload Characterization (IISWC) Pub Date : 2021-11-01 DOI: 10.1109/micro.2012.5

Derek Chiou

引用次数: 0

Understanding the applicability of CMP performance optimizations on data mining applications 了解CMP性能优化在数据挖掘应用程序上的适用性

2009 IEEE International Symposium on Workload Characterization (IISWC) Pub Date : 2009-10-04 DOI: 10.1109/IISWC.2009.5306779

Ivan Jibaja, K. Shaw

引用次数: 2

Understanding PARSEC performance on contemporary CMPs 了解PARSEC在当代cmp上的性能

2009 IEEE International Symposium on Workload Characterization (IISWC) Pub Date : 2009-10-04 DOI: 10.1109/IISWC.2009.5306793

M. Bhadauria, Vincent M. Weaver, S. Mckee

{"title":"Understanding PARSEC performance on contemporary CMPs","authors":"M. Bhadauria, Vincent M. Weaver, S. Mckee","doi":"10.1109/IISWC.2009.5306793","DOIUrl":"https://doi.org/10.1109/IISWC.2009.5306793","url":null,"abstract":"PARSEC is a reference application suite used in industry and academia to assess new Chip Multiprocessor (CMP) designs. No investigation to date has profiled PARSEC on real hardware to better understand scaling properties and bottlenecks. This understanding is crucial in guiding future CMP designs for these kinds of emerging workloads. We use hardware performance counters, taking a systems-level approach and varying common architectural parameters: number of out-of-order cores, memory hierarchy configurations, number of multiple simultaneous threads, number of memory channels, and processor frequencies. We find these programs to be largely compute-bound, and thus limited by number of cores, micro-architectural resources, and cache-to-cache transfers, rather than by off-chip memory or system bus bandwidth. Half the suite fails to scale linearly with increasing number of threads, and some applications saturate performance at few threads on all platforms tested. Exploiting thread level parallelism delivers greater payoffs than exploiting instruction level parallelism. To reduce power and improve performance, we recommend increasing the number of arithmetic units per core, increasing support for TLP, and reducing support for ILP.","PeriodicalId":387816,"journal":{"name":"2009 IEEE International Symposium on Workload Characterization (IISWC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126890333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 86

Analyzing and improving performance scalability of commercial server workloads on a chip multiprocessor 在芯片多处理器上分析和改进商业服务器工作负载的性能可伸缩性

2009 IEEE International Symposium on Workload Characterization (IISWC) Pub Date : 2009-10-04 DOI: 10.1109/IISWC.2009.5306781

K. Ishizaki, T. Nakatani, S. Daijavad

{"title":"Analyzing and improving performance scalability of commercial server workloads on a chip multiprocessor","authors":"K. Ishizaki, T. Nakatani, S. Daijavad","doi":"10.1109/IISWC.2009.5306781","DOIUrl":"https://doi.org/10.1109/IISWC.2009.5306781","url":null,"abstract":"A chip multiprocessor (CMP) with many low performance cores can achieve high performance or high performance/power for commercial server applications. The large number of hardware threads of a CMP with many low performance cores poses significant challenges to application developers in writing scalable applications. Many papers have assessed the architectural characteristics and the performance scalability, and some of them have identified lock contention as one of the scalability bottlenecks. However, there are few studies that resolved these problems, analyzed their causes, and compared the architectural characteristics before and after the scalability limitations were addressed. We analyzed and resolved some of the problems limiting the scalability of three commercial server applications with 64 hardware threads. We also did before and after comparisons of the architectural characteristics affected by the scalability enhancements, supporting the development of new processors. We addressed the lock contention with changes in the Java code. Our enhancements improved the performance scalability by up to 132%. We show that though the causes of lock contention are in different software layers, they share certain similarities and can be organized in three categories. Our comparisons reveal that the CPI and data TLB miss rates decrease, but the L2 data cache miss rates, L2 instruction cache miss rates, and memory traffic increase. These results suggest that we need to address the performance scalability problems of an application before we can accurately measure the architectural characteristics of a CMP.","PeriodicalId":387816,"journal":{"name":"2009 IEEE International Symposium on Workload Characterization (IISWC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123880234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

A characterization and analysis of PTX kernels PTX核的性质与分析

2009 IEEE International Symposium on Workload Characterization (IISWC) Pub Date : 2009-10-04 DOI: 10.1109/IISWC.2009.5306801

Andrew Kerr, G. Diamos, S. Yalamanchili

{"title":"A characterization and analysis of PTX kernels","authors":"Andrew Kerr, G. Diamos, S. Yalamanchili","doi":"10.1109/IISWC.2009.5306801","DOIUrl":"https://doi.org/10.1109/IISWC.2009.5306801","url":null,"abstract":"General purpose application development for GPUs (GPGPU) has recently gained momentum as a cost-effective approach for accelerating data- and compute-intensive applications. It has been driven by the introduction of C-based programming environments such as NVIDIA's CUDA [1], OpenCL [2], and Intel's Ct [3]. While significant effort has been focused on developing and evaluating applications and software tools, comparatively little has been devoted to the analysis and characterization of applications to assist future work in compiler optimizations, application re-structuring, and micro-architecture design. This paper proposes a set of metrics for GPU workloads and uses these metrics to analyze the behavior of GPU programs. We report on an analysis of over 50 kernels and applications including the full NVIDIA CUDA SDK and UIUC's Parboil Benchmark Suite covering control flow, data flow, parallelism, and memory behavior. The analysis was performed using a full function emulator we developed that implements the NVIDIA virtual machine referred to as PTX (Parallel Thread eXecution architecture) - a machine model and low level virtual ISA that is representative of ISAs for data parallel execution. The emulator can execute compiled kernels from the CUDA compiler, currently supports the full PTX 1.4 specification [4], and has been validated against the full CUDA SDK. The results quantify the importance of optimizations such as those for branch reconvergence, the prevalance of sharing between threads, and highlights opportunities for additional parallelism.","PeriodicalId":387816,"journal":{"name":"2009 IEEE International Symposium on Workload Characterization (IISWC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127650904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 135

Characterization of DBT overhead DBT开销的表征

2009 IEEE International Symposium on Workload Characterization (IISWC) Pub Date : 2009-10-04 DOI: 10.1109/IISWC.2009.5306785

E. Borin, Youfeng Wu

引用次数: 26

Workload characterization and optimization of high-performance text indexing on the Cell Broadband Engine™ (Cell/B.E.) Cell宽带引擎™(Cell/B.E.)上高性能文本索引的工作负载表征和优化

2009 IEEE International Symposium on Workload Characterization (IISWC) Pub Date : 2009-10-04 DOI: 10.1109/IISWC.2009.5306798

D. Scarpazza, G. W. Braudaway

引用次数: 9

Green clouds and black swans in the exascale era 百亿亿次时代的绿云和黑天鹅

2009 IEEE International Symposium on Workload Characterization (IISWC) Pub Date : 2009-10-04 DOI: 10.1109/IISWC.2009.5306800

Parthasarathy Ranganathan

引用次数: 1

Experimental evaluation of N-tier systems: Observation and analysis of multi-bottlenecks n层系统的实验评估:多瓶颈的观察与分析

2009 IEEE International Symposium on Workload Characterization (IISWC) Pub Date : 2009-10-04 DOI: 10.1109/IISWC.2009.5306791

Simon Malkowski, Markus Hedwig, C. Pu

{"title":"Experimental evaluation of N-tier systems: Observation and analysis of multi-bottlenecks","authors":"Simon Malkowski, Markus Hedwig, C. Pu","doi":"10.1109/IISWC.2009.5306791","DOIUrl":"https://doi.org/10.1109/IISWC.2009.5306791","url":null,"abstract":"In many areas such as e-commerce, mission-critical N-tier applications have grown increasingly complex. They are characterized by non-stationary workloads (e.g., peak load several times the sustained load) and complex dependencies among the component servers. We have studied N-tier applications through a large number of experiments using the RUBiS and RUBBoS benchmarks. We apply statistical methods such as kernel density estimation, adaptive filtering, and change detection through multiple-model hypothesis tests to analyze more than 200GB of recorded data. Beyond the usual single-bottlenecks, we have observed more intricate bottleneck phenomena. For instance, in several configurations all system components show average resource utilization significantly below saturation, but overall throughput is limited despite addition of more resources. More concretely, our analysis shows experimental evidence of multi-bottleneck cases with low average resource utilization where several resources saturate alternatively, indicating a clear lack of independence in their utilization. Our data corroborates the increasing awareness of the need for more sophisticated analytical performance models to describe N-tier applications that do not rely on independent resource utilization assumptions. We also present a preliminary taxonomy of multi-bottlenecks found in our experimentally observed data.","PeriodicalId":387816,"journal":{"name":"2009 IEEE International Symposium on Workload Characterization (IISWC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117169037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 69